mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-19 07:11:22 +03:00
Update sys.
This commit is contained in:
Sorgelig
@ -226,7 +226,7 @@ video_calc video_calc
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.new_vmode(new_vmode),
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.video_rotated(video_rotated),
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.par_num(byte_cnt[3:0]),
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.par_num(byte_cnt[4:0]),
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.dout(vc_dout)
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);
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@ -502,7 +502,7 @@ always@(posedge clk_sys) begin : uio_block
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'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
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//Video res.
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'h23: if(!byte_cnt[MAX_W:4]) io_dout <= vc_dout;
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'h23: if(!byte_cnt[MAX_W:5]) io_dout <= vc_dout;
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//RTC
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'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
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@ -872,7 +872,7 @@ module video_calc
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input new_vmode,
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input video_rotated,
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input [3:0] par_num,
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input [4:0] par_num,
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output reg [15:0] dout
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);
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@ -893,6 +893,9 @@ always @(posedge clk_sys) begin
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13: dout <= vid_vtime_hdmi[31:16];
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14: dout <= vid_ccnt[15:0];
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15: dout <= vid_ccnt[31:16];
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16: dout <= vid_pixrep;
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17: dout <= vid_de_h;
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18: dout <= vid_de_v;
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default dout <= 0;
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endcase
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end
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@ -902,24 +905,44 @@ reg [31:0] vid_vcnt = 0;
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reg [31:0] vid_ccnt = 0;
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reg [7:0] vid_nres = 0;
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reg [1:0] vid_int = 0;
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reg [7:0] vid_pixrep;
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reg [15:0] vid_de_h;
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reg [7:0] vid_de_v;
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always @(posedge clk_vid) begin
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integer hcnt;
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integer vcnt;
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integer ccnt;
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reg old_vs= 0, old_de = 0, old_vmode = 0;
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reg [7:0] pcnt;
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reg [7:0] de_v;
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reg [15:0] de_h;
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reg old_vs = 0, old_hs = 0, old_hs_vclk = 0, old_de = 0, old_de_vclk = 0, old_de1 = 0, old_vmode = 0;
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reg [3:0] resto = 0;
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reg calch = 0;
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if(calch & de) ccnt <= ccnt + 1;
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pcnt <= pcnt + 1'd1;
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old_hs_vclk <= hs;
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de_h <= de_h + 1'd1;
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if(old_hs_vclk & ~hs) de_h <= 1;
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old_de_vclk <= de;
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if(calch & ~old_de_vclk & de) vid_de_h <= de_h;
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if(ce_pix) begin
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old_vs <= vs;
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old_hs <= hs;
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old_de <= de;
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old_de1 <= old_de;
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pcnt <= 1;
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if(~vs & ~old_de & de) vcnt <= vcnt + 1;
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if(calch & de) hcnt <= hcnt + 1;
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if(old_de & ~de) calch <= 0;
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if(~old_de1 & old_de) vid_pixrep <= pcnt;
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if(old_hs & ~hs) de_v <= de_v + 1'd1;
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if(calch & ~old_de & de) vid_de_v <= de_v;
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if(old_vs & ~vs) begin
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vid_int <= {vid_int[0],f1};
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@ -939,6 +962,7 @@ always @(posedge clk_vid) begin
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hcnt <= 0;
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ccnt <= 0;
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calch <= 1;
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de_v <= 0;
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end
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end
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end
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@ -8,7 +8,9 @@ module mcp23009
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output reg [2:0] btn,
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input [2:0] led,
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output reg sd_cd,
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output reg flg_sd_cd,
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output reg flg_present,
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output reg flg_mode,
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output scl,
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inout sda
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@ -50,7 +52,9 @@ always@(posedge clk) begin
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idx <= 0;
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btn <= 0;
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rw <= 0;
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sd_cd <= 1;
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flg_sd_cd <= 1;
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flg_present <= 0;
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flg_mode <= 1;
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end
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else begin
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if(~&init_data[idx]) begin
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@ -84,7 +88,10 @@ always@(posedge clk) begin
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state <= 0;
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rw <= 0;
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if(!error) begin
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if(rw) {sd_cd, btn} <= {dout[7], dout[5:3]};
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if(rw) begin
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{flg_sd_cd, flg_mode, btn} <= {dout[7:3]};
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flg_present <= 1;
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end
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rw <= ~rw;
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end
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end
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@ -1,44 +1,5 @@
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"
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set_global_assignment -library "pll_cfg" -name MISC_FILE [file join $::quartus(qip_path) "pll_cfg.cmp"]
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_QSYS_MODE "UNKNOWN"
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set_global_assignment -name SYNTHESIS_ONLY_QIP ON
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_NAME "cGxsX2hkbWlfY2Zn"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ=="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
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set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg.v"]
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set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg.v"]
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set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg_hdmi.v"]
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set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_top.v"]
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set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_core.v"]
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"
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@ -16,7 +16,7 @@
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module altera_pll_reconfig_core
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#(
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parameter reconf_width = 64,
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parameter device_family = "Stratix V",
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parameter device_family = "Cyclone V",
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// MIF Streaming parameters
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parameter RECONFIG_ADDR_WIDTH = 6,
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parameter RECONFIG_DATA_WIDTH = 32,
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@ -1883,7 +1883,7 @@ module fpll_dprio_init (
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endmodule
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module dyn_phase_shift
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#(
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parameter device_family = "Stratix V"
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parameter device_family = "Cyclone V"
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) (
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input wire clk,
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@ -2112,7 +2112,7 @@ endmodule
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module generic_lcell_comb
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#(
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//parameter
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parameter family = "Stratix V",
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parameter family = "Cyclone V",
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parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
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parameter dont_touch = "on"
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) (
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@ -16,7 +16,7 @@
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module altera_pll_reconfig_top
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#(
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parameter reconf_width = 64,
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parameter device_family = "Stratix V",
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parameter device_family = "Cyclone V",
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parameter RECONFIG_ADDR_WIDTH = 6,
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parameter RECONFIG_DATA_WIDTH = 32,
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1282
sys/pll_cfg/pll_cfg_hdmi.v
Normal file
1282
sys/pll_cfg/pll_cfg_hdmi.v
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,4 @@
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set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ]
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set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ]
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set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ]
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set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ]
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@ -16,13 +16,6 @@ set_location_assignment PIN_V10 -to ADC_SCK
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set_location_assignment PIN_AC4 -to ADC_SDI
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set_location_assignment PIN_AD4 -to ADC_SDO
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#============================================================
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# ARDUINO
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#============================================================
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
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#============================================================
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# I2C LEDS/BUTTONS
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#============================================================
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@ -25,6 +25,7 @@ set_false_path -from [get_ports {KEY*}]
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set_false_path -from [get_ports {BTN_*}]
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set_false_path -to [get_ports {LED_*}]
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set_false_path -to [get_ports {VGA_*}]
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set_false_path -from [get_ports {VGA_EN}]
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set_false_path -to [get_ports {AUDIO_SPDIF}]
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set_false_path -to [get_ports {AUDIO_L}]
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set_false_path -to [get_ports {AUDIO_R}]
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@ -34,6 +35,7 @@ set_false_path -from {cfg[*]}
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set_false_path -from {VSET[*]}
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set_false_path -to {wcalc[*] hcalc[*]}
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set_false_path -to {hdmi_width[*] hdmi_height[*]}
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set_false_path -to {deb_* btn_en btn_up}
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set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
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set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
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@ -58,6 +60,7 @@ set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
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set_false_path -from {aflt_* acx* acy* areset* arc*}
|
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set_false_path -from {arx* ary*}
|
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set_false_path -from {vs_line*}
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set_false_path -from {ColorBurst_Range* PhaseInc* pal_en cvbs yc_en}
|
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set_false_path -from {ascal|o_ihsize*}
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set_false_path -from {ascal|o_ivsize*}
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@ -70,4 +73,5 @@ set_false_path -from {ascal|o_htotal* ascal|o_vtotal*}
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set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*}
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set_false_path -from {ascal|o_hsize* ascal|o_vsize*}
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set_false_path -from {mcp23009|sd_cd}
|
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set_false_path -from {mcp23009|flg_*}
|
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set_false_path -to {sysmem|fpga_interfaces|clocks_resets*}
|
||||
|
||||
468
sys/sys_top.v
468
sys/sys_top.v
@ -72,7 +72,7 @@ module sys_top
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output [5:0] VGA_R,
|
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output [5:0] VGA_G,
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output [5:0] VGA_B,
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||||
inout VGA_HS, // VGA_HS is secondary SD card detect when VGA_EN = 1 (inactive)
|
||||
inout VGA_HS,
|
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output VGA_VS,
|
||||
input VGA_EN, // active low
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||||
|
||||
@ -124,35 +124,24 @@ module sys_top
|
||||
inout [6:0] USER_IO
|
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);
|
||||
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||||
`ifdef MISTER_DUAL_SDRAM
|
||||
`ifndef MISTER_DISABLE_YC
|
||||
`define MISTER_DISABLE_YC
|
||||
`endif
|
||||
`endif
|
||||
|
||||
////////////////////// Secondary SD ///////////////////////////////////
|
||||
wire SD_CS, SD_CLK, SD_MOSI;
|
||||
wire SD_CS, SD_CLK, SD_MOSI, SD_MISO, SD_CD;
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||||
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||||
`ifndef MISTER_DUAL_SDRAM
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||||
wire sd_miso = SW[3] | SDIO_DAT[0];
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||||
`else
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||||
wire sd_miso = 1;
|
||||
`endif
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||||
wire SD_MISO = mcp_sdcd ? sd_miso : SD_SPI_MISO;
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||||
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||||
`ifndef MISTER_DUAL_SDRAM
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||||
assign SDIO_DAT[2:1]= 2'bZZ;
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||||
assign SDIO_DAT[3] = SW[3] ? 1'bZ : SD_CS;
|
||||
assign SDIO_CLK = SW[3] ? 1'bZ : SD_CLK;
|
||||
assign SDIO_CMD = SW[3] ? 1'bZ : SD_MOSI;
|
||||
assign SD_SPI_CS = mcp_sdcd ? ((~VGA_EN & sog & ~cs1) ? 1'b1 : 1'bZ) : SD_CS;
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||||
assign SD_CD = mcp_en ? mcp_sdcd : SDCD_SPDIF;
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||||
assign SD_MISO = SD_CD | (mcp_en ? SD_SPI_MISO : (VGA_EN | SDIO_DAT[0]));
|
||||
assign SD_SPI_CS = mcp_en ? (mcp_sdcd ? 1'bZ : SD_CS) : (sog & ~cs1 & ~VGA_EN) ? 1'b1 : 1'bZ;
|
||||
assign SD_SPI_CLK = (~mcp_en | mcp_sdcd) ? 1'bZ : SD_CLK;
|
||||
assign SD_SPI_MOSI = (~mcp_en | mcp_sdcd) ? 1'bZ : SD_MOSI;
|
||||
assign {SDIO_CLK,SDIO_CMD,SDIO_DAT} = av_dis ? 6'bZZZZZZ : (mcp_en | (SDCD_SPDIF & ~SW[2])) ? {vga_g,vga_r,vga_b} : {SD_CLK,SD_MOSI,SD_CS,3'bZZZ};
|
||||
`else
|
||||
assign SD_CD = mcp_sdcd;
|
||||
assign SD_MISO = mcp_sdcd | SD_SPI_MISO;
|
||||
assign SD_SPI_CS = mcp_sdcd ? 1'bZ : SD_CS;
|
||||
assign SD_SPI_CLK = mcp_sdcd ? 1'bZ : SD_CLK;
|
||||
assign SD_SPI_MOSI = mcp_sdcd ? 1'bZ : SD_MOSI;
|
||||
`endif
|
||||
|
||||
assign SD_SPI_CLK = mcp_sdcd ? 1'bZ : SD_CLK;
|
||||
assign SD_SPI_MOSI = mcp_sdcd ? 1'bZ : SD_MOSI;
|
||||
|
||||
////////////////////// LEDs/Buttons ///////////////////////////////////
|
||||
|
||||
reg [7:0] led_overtake = 0;
|
||||
@ -163,36 +152,59 @@ wire led_d = led_disk[1] ? ~led_disk[0] : ~(led_disk[0] | gp_out[29]);
|
||||
wire led_u = ~led_user;
|
||||
wire led_locked;
|
||||
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
assign LED_POWER = (SW[3] | led_p) ? 1'bZ : 1'b0;
|
||||
assign LED_HDD = (SW[3] | led_d) ? 1'bZ : 1'b0;
|
||||
assign LED_USER = (SW[3] | led_u) ? 1'bZ : 1'b0;
|
||||
`endif
|
||||
|
||||
//LEDs on main board
|
||||
//LEDs on de10-nano board
|
||||
assign LED = (led_overtake & led_state) | (~led_overtake & {1'b0,led_locked,1'b0, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u});
|
||||
|
||||
wire btn_r, btn_o, btn_u;
|
||||
`ifdef MISTER_DUAL_SDRAM
|
||||
assign {btn_r,btn_o,btn_u} = SW[3] ? {mcp_btn[1],mcp_btn[2],mcp_btn[0]} : ~{SDRAM2_DQ[9],SDRAM2_DQ[13],SDRAM2_DQ[11]};
|
||||
`else
|
||||
assign {btn_r,btn_o,btn_u} = ~{BTN_RESET,BTN_OSD,BTN_USER} | {mcp_btn[1],mcp_btn[2],mcp_btn[0]};
|
||||
`endif
|
||||
|
||||
wire [2:0] mcp_btn;
|
||||
wire mcp_sdcd;
|
||||
wire mcp_en;
|
||||
wire mcp_mode;
|
||||
mcp23009 mcp23009
|
||||
(
|
||||
.clk(FPGA_CLK2_50),
|
||||
|
||||
.btn(mcp_btn),
|
||||
.led({led_p, led_d, led_u}),
|
||||
.sd_cd(mcp_sdcd),
|
||||
.flg_sd_cd(mcp_sdcd),
|
||||
.flg_present(mcp_en),
|
||||
.flg_mode(mcp_mode),
|
||||
|
||||
.scl(IO_SCL),
|
||||
.sda(IO_SDA)
|
||||
);
|
||||
|
||||
wire io_dig = mcp_en ? mcp_mode : SW[3];
|
||||
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire av_dis = io_dig | VGA_EN;
|
||||
assign LED_POWER = av_dis ? 1'bZ : mcp_en ? de1 : led_p ? 1'bZ : 1'b0;
|
||||
assign LED_HDD = av_dis ? 1'bZ : mcp_en ? (sog & ~cs1) : led_d ? 1'bZ : 1'b0;
|
||||
//assign LED_USER = av_dis ? 1'bZ : mcp_en ? ~vga_tx_clk : led_u ? 1'bZ : 1'b0;
|
||||
assign LED_USER = VGA_TX_CLK;
|
||||
wire BTN_DIS = VGA_EN;
|
||||
`else
|
||||
wire BTN_RESET = SDRAM2_DQ[9];
|
||||
wire BTN_OSD = SDRAM2_DQ[13];
|
||||
wire BTN_USER = SDRAM2_DQ[11];
|
||||
wire BTN_DIS = SDRAM2_DQ[15];
|
||||
`endif
|
||||
|
||||
reg BTN_EN = 0;
|
||||
reg [25:0] btn_timeout = 0;
|
||||
initial btn_timeout = 0;
|
||||
always @(posedge FPGA_CLK2_50) begin
|
||||
reg btn_up = 0;
|
||||
reg btn_en = 0;
|
||||
|
||||
btn_up <= BTN_RESET & BTN_OSD & BTN_USER;
|
||||
if(~reset & btn_up & ~&btn_timeout) btn_timeout <= btn_timeout + 1'd1;
|
||||
btn_en <= ~BTN_DIS;
|
||||
BTN_EN <= &btn_timeout & btn_en;
|
||||
end
|
||||
|
||||
wire btn_r = (mcp_en | SW[3]) ? mcp_btn[1] : (BTN_EN & ~BTN_RESET);
|
||||
wire btn_o = (mcp_en | SW[3]) ? mcp_btn[2] : (BTN_EN & ~BTN_OSD );
|
||||
wire btn_u = (mcp_en | SW[3]) ? mcp_btn[0] : (BTN_EN & ~BTN_USER );
|
||||
|
||||
reg btn_user, btn_osd;
|
||||
always @(posedge FPGA_CLK2_50) begin
|
||||
@ -218,7 +230,7 @@ end
|
||||
|
||||
// gp_in[31] = 0 - quick flag that FPGA is initialized (HPS reads 1 when FPGA is not in user mode)
|
||||
// used to avoid lockups while JTAG loading
|
||||
wire [31:0] gp_in = {1'b0, btn_user | btn[1], btn_osd | btn[0], SW[3], 8'd0, io_ver, io_ack, io_wide, io_dout | io_dout_sys};
|
||||
wire [31:0] gp_in = {1'b0, btn_user | btn[1], btn_osd | btn[0], io_dig, 8'd0, io_ver, io_ack, io_wide, io_dout | io_dout_sys};
|
||||
wire [31:0] gp_out;
|
||||
|
||||
wire [1:0] io_ver = 1; // 0 - obsolete. 1 - optimized HPS I/O. 2,3 - reserved for future.
|
||||
@ -232,7 +244,7 @@ wire io_ss1 = gp_outr[19];
|
||||
wire io_ss2 = gp_outr[20];
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
wire io_osd_hdmi = io_ss1 & ~io_ss0;
|
||||
wire io_osd_hdmi = io_ss1 & ~io_ss0;
|
||||
`endif
|
||||
|
||||
wire io_fpga = ~io_ss1 & io_ss0;
|
||||
@ -273,14 +285,14 @@ cyclonev_hps_interface_mpu_general_purpose h2f_gp
|
||||
|
||||
|
||||
reg [15:0] cfg;
|
||||
|
||||
reg cfg_set = 0;
|
||||
wire vga_fb = cfg[12] | vga_force_scaler;
|
||||
|
||||
`ifdef MISTER_DEBUG_NOHDMI
|
||||
wire direct_video = 1;
|
||||
wire vga_fb = 0;
|
||||
wire direct_video = 1;
|
||||
`else
|
||||
wire direct_video = cfg[10];
|
||||
wire vga_fb = cfg[12] | vga_force_scaler;
|
||||
wire direct_video = cfg[10];
|
||||
`endif
|
||||
|
||||
wire audio_96k = cfg[6];
|
||||
@ -289,7 +301,11 @@ wire io_osd_vga = io_ss1 & ~io_ss2;
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire ypbpr_en = cfg[5];
|
||||
wire sog = cfg[9];
|
||||
`ifdef MISTER_DEBUG_NOHDMI
|
||||
wire vga_scaler = 0;
|
||||
`else
|
||||
wire vga_scaler = cfg[2] | vga_force_scaler;
|
||||
`endif
|
||||
`endif
|
||||
|
||||
reg cfg_custom_t = 0;
|
||||
@ -663,35 +679,35 @@ wire hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl, hdmi_brd;
|
||||
wire freeze;
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
wire clk_hdmi = hdmi_clk_out;
|
||||
wire clk_hdmi = hdmi_clk_out;
|
||||
|
||||
ascal
|
||||
#(
|
||||
ascal
|
||||
#(
|
||||
.RAMBASE(32'h20000000),
|
||||
`ifdef MISTER_SMALL_VBUF
|
||||
`ifdef MISTER_SMALL_VBUF
|
||||
.RAMSIZE(32'h00200000),
|
||||
`else
|
||||
`else
|
||||
.RAMSIZE(32'h00800000),
|
||||
`endif
|
||||
`ifndef MISTER_FB
|
||||
`endif
|
||||
`ifndef MISTER_FB
|
||||
.PALETTE2("false"),
|
||||
`else
|
||||
`else
|
||||
`ifndef MISTER_FB_PALETTE
|
||||
.PALETTE2("false"),
|
||||
`endif
|
||||
`endif
|
||||
`ifdef MISTER_DISABLE_ADAPTIVE
|
||||
`endif
|
||||
`ifdef MISTER_DISABLE_ADAPTIVE
|
||||
.ADAPTIVE("false"),
|
||||
`endif
|
||||
`ifdef MISTER_DOWNSCALE_NN
|
||||
`endif
|
||||
`ifdef MISTER_DOWNSCALE_NN
|
||||
.DOWNSCALE_NN("true"),
|
||||
`endif
|
||||
`endif
|
||||
.FRAC(8),
|
||||
.N_DW(128),
|
||||
.N_AW(28)
|
||||
)
|
||||
ascal
|
||||
(
|
||||
)
|
||||
ascal
|
||||
(
|
||||
.reset_na (~reset_req),
|
||||
.run (1),
|
||||
.freeze (freeze),
|
||||
@ -748,7 +764,7 @@ ascal
|
||||
.pal1_a (pal_a),
|
||||
.pal1_wr (pal_wr),
|
||||
|
||||
`ifdef MISTER_FB
|
||||
`ifdef MISTER_FB
|
||||
`ifdef MISTER_FB_PALETTE
|
||||
.pal2_clk (fb_pal_clk),
|
||||
.pal2_dw (fb_pal_d),
|
||||
@ -757,7 +773,7 @@ ascal
|
||||
.pal2_wr (fb_pal_wr),
|
||||
.pal_n (fb_en),
|
||||
`endif
|
||||
`endif
|
||||
`endif
|
||||
|
||||
.o_fb_ena (FB_EN),
|
||||
.o_fb_hsize (FB_WIDTH),
|
||||
@ -776,7 +792,7 @@ ascal
|
||||
.avl_write (vbuf_write),
|
||||
.avl_read (vbuf_read),
|
||||
.avl_byteenable (vbuf_byteenable)
|
||||
);
|
||||
);
|
||||
`endif
|
||||
|
||||
reg LFB_EN = 0;
|
||||
@ -817,8 +833,8 @@ always @(posedge clk_sys) begin
|
||||
end
|
||||
|
||||
`ifdef MISTER_FB
|
||||
reg fb_vbl;
|
||||
always @(posedge clk_vid) fb_vbl <= hdmi_vbl;
|
||||
reg fb_vbl;
|
||||
always @(posedge clk_vid) fb_vbl <= hdmi_vbl;
|
||||
`endif
|
||||
|
||||
reg ar_md_start;
|
||||
@ -944,9 +960,9 @@ always @(posedge clk_vid) begin
|
||||
end
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
wire [15:0] lltune;
|
||||
pll_hdmi_adj pll_hdmi_adj
|
||||
(
|
||||
wire [15:0] lltune;
|
||||
pll_hdmi_adj pll_hdmi_adj
|
||||
(
|
||||
.clk(FPGA_CLK1_50),
|
||||
.reset_na(~reset_req),
|
||||
|
||||
@ -961,7 +977,7 @@ pll_hdmi_adj pll_hdmi_adj
|
||||
.o_write(cfg_write),
|
||||
.o_address(cfg_address),
|
||||
.o_writedata(cfg_data)
|
||||
);
|
||||
);
|
||||
`else
|
||||
assign led_locked = 0;
|
||||
`endif
|
||||
@ -987,15 +1003,15 @@ end
|
||||
|
||||
///////////////////////// HDMI output /////////////////////////////////
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
wire hdmi_clk_out;
|
||||
pll_hdmi pll_hdmi
|
||||
(
|
||||
wire hdmi_clk_out;
|
||||
pll_hdmi pll_hdmi
|
||||
(
|
||||
.refclk(FPGA_CLK1_50),
|
||||
.rst(reset_req),
|
||||
.reconfig_to_pll(reconfig_to_pll),
|
||||
.reconfig_from_pll(reconfig_from_pll),
|
||||
.outclk_0(hdmi_clk_out)
|
||||
);
|
||||
);
|
||||
`endif
|
||||
|
||||
//1920x1080@60 PCLK=148.5MHz CEA
|
||||
@ -1020,22 +1036,20 @@ reg [5:0] adj_address;
|
||||
reg [31:0] adj_data;
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
pll_cfg pll_cfg
|
||||
(
|
||||
pll_cfg_hdmi pll_cfg_hdmi
|
||||
(
|
||||
.mgmt_clk(FPGA_CLK1_50),
|
||||
.mgmt_reset(reset_req),
|
||||
.mgmt_waitrequest(cfg_waitrequest),
|
||||
.mgmt_read(0),
|
||||
.mgmt_readdata(),
|
||||
.mgmt_write(cfg_write),
|
||||
.mgmt_address(cfg_address),
|
||||
.mgmt_writedata(cfg_data),
|
||||
.reconfig_to_pll(reconfig_to_pll),
|
||||
.reconfig_from_pll(reconfig_from_pll)
|
||||
);
|
||||
);
|
||||
|
||||
reg cfg_got = 0;
|
||||
always @(posedge clk_sys) begin
|
||||
reg cfg_got = 0;
|
||||
always @(posedge clk_sys) begin
|
||||
reg vsd, vsd2;
|
||||
if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set;
|
||||
else begin
|
||||
@ -1043,10 +1057,10 @@ always @(posedge clk_sys) begin
|
||||
vsd2 <= vsd;
|
||||
if(~vsd2 & vsd) cfg_got <= cfg_set;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg cfg_ready = 0;
|
||||
always @(posedge FPGA_CLK1_50) begin
|
||||
reg cfg_ready = 0;
|
||||
always @(posedge FPGA_CLK1_50) begin
|
||||
reg gotd = 0, gotd2 = 0;
|
||||
reg custd = 0, custd2 = 0;
|
||||
reg old_wait = 0;
|
||||
@ -1072,12 +1086,9 @@ always @(posedge FPGA_CLK1_50) begin
|
||||
|
||||
old_wait <= adj_waitrequest;
|
||||
if(old_wait & ~adj_waitrequest & gotd) cfg_ready <= 1;
|
||||
end
|
||||
|
||||
end
|
||||
`else
|
||||
|
||||
wire cfg_ready = 1;
|
||||
|
||||
wire cfg_ready = 1;
|
||||
`endif
|
||||
|
||||
assign HDMI_I2C_SCL = hdmi_scl_en ? 1'b0 : 1'bZ;
|
||||
@ -1093,26 +1104,25 @@ cyclonev_hps_interface_peripheral_i2c hdmi_i2c
|
||||
);
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
|
||||
`ifdef MISTER_FB
|
||||
reg dis_output;
|
||||
always @(posedge clk_hdmi) begin
|
||||
`ifdef MISTER_FB
|
||||
reg dis_output;
|
||||
always @(posedge clk_hdmi) begin
|
||||
reg dis;
|
||||
dis <= fb_force_blank & ~LFB_EN;
|
||||
dis_output <= dis;
|
||||
end
|
||||
`else
|
||||
wire dis_output = 0;
|
||||
`endif
|
||||
end
|
||||
`else
|
||||
wire dis_output = 0;
|
||||
`endif
|
||||
|
||||
wire [23:0] hdmi_data_mask;
|
||||
wire hdmi_de_mask, hdmi_vs_mask, hdmi_hs_mask;
|
||||
wire [23:0] hdmi_data_mask;
|
||||
wire hdmi_de_mask, hdmi_vs_mask, hdmi_hs_mask;
|
||||
|
||||
reg [15:0] shadowmask_data;
|
||||
reg shadowmask_wr = 0;
|
||||
reg [15:0] shadowmask_data;
|
||||
reg shadowmask_wr = 0;
|
||||
|
||||
shadowmask HDMI_shadowmask
|
||||
(
|
||||
shadowmask HDMI_shadowmask
|
||||
(
|
||||
.clk(clk_hdmi),
|
||||
.clk_sys(clk_sys),
|
||||
|
||||
@ -1130,13 +1140,13 @@ shadowmask HDMI_shadowmask
|
||||
.hs_out(hdmi_hs_mask),
|
||||
.vs_out(hdmi_vs_mask),
|
||||
.de_out(hdmi_de_mask)
|
||||
);
|
||||
);
|
||||
|
||||
wire [23:0] hdmi_data_osd;
|
||||
wire hdmi_de_osd, hdmi_vs_osd, hdmi_hs_osd;
|
||||
wire [23:0] hdmi_data_osd;
|
||||
wire hdmi_de_osd, hdmi_vs_osd, hdmi_hs_osd;
|
||||
|
||||
osd hdmi_osd
|
||||
(
|
||||
osd hdmi_osd
|
||||
(
|
||||
.clk_sys(clk_sys),
|
||||
|
||||
.io_osd(io_osd_hdmi),
|
||||
@ -1153,11 +1163,11 @@ osd hdmi_osd
|
||||
.hs_out(hdmi_hs_osd),
|
||||
.vs_out(hdmi_vs_osd),
|
||||
.de_out(hdmi_de_osd)
|
||||
);
|
||||
`endif
|
||||
);
|
||||
|
||||
wire hdmi_cs_osd;
|
||||
csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd);
|
||||
wire hdmi_cs_osd;
|
||||
csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd);
|
||||
`endif
|
||||
|
||||
reg [23:0] dv_data;
|
||||
reg dv_hs, dv_vs, dv_de;
|
||||
@ -1191,11 +1201,12 @@ always @(posedge clk_vid) begin
|
||||
end
|
||||
|
||||
dv_de1 <= !{hss,dv_hs_osd} && vde;
|
||||
dv_hs1 <= csync_en ? dv_cs_osd : dv_hs_osd;
|
||||
dv_vs1 <= dv_vs_osd;
|
||||
end
|
||||
|
||||
dv_d1 <= dv_data_osd;
|
||||
dv_hs1 <= csync_en ? dv_cs_osd : dv_hs_osd;
|
||||
dv_vs1 <= dv_vs_osd;
|
||||
|
||||
dv_d2 <= dv_d1;
|
||||
dv_de2 <= dv_de1;
|
||||
dv_hs2 <= dv_hs1;
|
||||
@ -1208,21 +1219,21 @@ always @(posedge clk_vid) begin
|
||||
end
|
||||
|
||||
`ifndef MISTER_DISABLE_YC
|
||||
assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = ~yc_en ? {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd } : {yc_o, yc_hs, yc_vs, yc_cs };
|
||||
assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = ~yc_en ? {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd } : {yc_o, yc_hs, yc_vs, yc_cs };
|
||||
`else
|
||||
assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd };
|
||||
assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd };
|
||||
`endif
|
||||
|
||||
wire hdmi_tx_clk;
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
cyclonev_clkselect hdmi_clk_sw
|
||||
(
|
||||
cyclonev_clkselect hdmi_clk_sw
|
||||
(
|
||||
.clkselect({1'b1, ~vga_fb & direct_video}),
|
||||
.inclk({clk_vid, hdmi_clk_out, 2'b00}),
|
||||
.outclk(hdmi_tx_clk)
|
||||
);
|
||||
);
|
||||
`else
|
||||
assign hdmi_tx_clk = clk_vid;
|
||||
assign hdmi_tx_clk = clk_vid;
|
||||
`endif
|
||||
|
||||
altddio_out
|
||||
@ -1267,10 +1278,17 @@ always @(posedge hdmi_tx_clk) begin
|
||||
hdmi_dv_vs <= dv_vs;
|
||||
hdmi_dv_de <= dv_de;
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
hs <= (~vga_fb & direct_video) ? hdmi_dv_hs : (direct_video & csync_en) ? hdmi_cs_osd : hdmi_hs_osd;
|
||||
vs <= (~vga_fb & direct_video) ? hdmi_dv_vs : hdmi_vs_osd;
|
||||
de <= (~vga_fb & direct_video) ? hdmi_dv_de : hdmi_de_osd;
|
||||
d <= (~vga_fb & direct_video) ? hdmi_dv_data : hdmi_data_osd;
|
||||
`else
|
||||
hs <= hdmi_dv_hs;
|
||||
vs <= hdmi_dv_vs;
|
||||
de <= hdmi_dv_de;
|
||||
d <= hdmi_dv_data;
|
||||
`endif
|
||||
|
||||
hdmi_out_hs <= hs;
|
||||
hdmi_out_vs <= vs;
|
||||
@ -1285,6 +1303,46 @@ assign HDMI_TX_D = hdmi_out_d;
|
||||
|
||||
///////////////////////// VGA output //////////////////////////////////
|
||||
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire vga_tx_clk;
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
cyclonev_clkselect vga_clk_sw
|
||||
(
|
||||
.clkselect({1'b1, ~vga_fb & ~vga_scaler}),
|
||||
.inclk({clk_vid, hdmi_clk_out, 2'b00}),
|
||||
.outclk(vga_tx_clk)
|
||||
);
|
||||
`else
|
||||
assign vga_tx_clk = clk_vid;
|
||||
`endif
|
||||
|
||||
wire VGA_TX_CLK;
|
||||
altddio_out
|
||||
#(
|
||||
.extend_oe_disable("OFF"),
|
||||
.intended_device_family("Cyclone V"),
|
||||
.invert_output("OFF"),
|
||||
.lpm_hint("UNUSED"),
|
||||
.lpm_type("altddio_out"),
|
||||
.oe_reg("UNREGISTERED"),
|
||||
.power_up_high("OFF"),
|
||||
.width(1)
|
||||
)
|
||||
vgaclk_ddr
|
||||
(
|
||||
.datain_h(1'b0),
|
||||
.datain_l(1'b1),
|
||||
.outclock(vga_tx_clk),
|
||||
.dataout(VGA_TX_CLK),
|
||||
.aclr(~mcp_en & ~av_dis),
|
||||
.aset(1'b0),
|
||||
.oe(~av_dis & (mcp_en | ~led_u)),
|
||||
.outclocken(1'b1),
|
||||
.sclr(1'b0),
|
||||
.sset(1'b0)
|
||||
);
|
||||
`endif
|
||||
|
||||
wire [23:0] vga_data_sl;
|
||||
wire vga_de_sl, vga_ce_sl, vga_vs_sl, vga_hs_sl;
|
||||
scanlines #(0) VGA_scanlines
|
||||
@ -1306,7 +1364,7 @@ scanlines #(0) VGA_scanlines
|
||||
);
|
||||
|
||||
wire [23:0] vga_data_osd;
|
||||
wire vga_vs_osd, vga_hs_osd;
|
||||
wire vga_vs_osd, vga_hs_osd, vga_de_osd;
|
||||
osd vga_osd
|
||||
(
|
||||
.clk_sys(clk_sys),
|
||||
@ -1324,46 +1382,13 @@ osd vga_osd
|
||||
|
||||
.dout(vga_data_osd),
|
||||
.hs_out(vga_hs_osd),
|
||||
.vs_out(vga_vs_osd)
|
||||
.vs_out(vga_vs_osd),
|
||||
.de_out(vga_de_osd)
|
||||
);
|
||||
|
||||
wire vga_cs_osd;
|
||||
csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
|
||||
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire VGA_DISABLE;
|
||||
wire [23:0] vgas_o;
|
||||
wire vgas_hs, vgas_vs, vgas_cs;
|
||||
vga_out vga_scaler_out
|
||||
(
|
||||
.clk(clk_hdmi),
|
||||
.ypbpr_en(ypbpr_en),
|
||||
.hsync(hdmi_hs_osd),
|
||||
.vsync(hdmi_vs_osd),
|
||||
.csync(hdmi_cs_osd),
|
||||
.dout(vgas_o),
|
||||
.din({24{hdmi_de_osd}} & hdmi_data_osd),
|
||||
.hsync_o(vgas_hs),
|
||||
.vsync_o(vgas_vs),
|
||||
.csync_o(vgas_cs)
|
||||
);
|
||||
|
||||
wire [23:0] vga_o, vga_o_t;
|
||||
wire vga_hs, vga_vs, vga_cs, vga_hs_t, vga_vs_t, vga_cs_t;
|
||||
vga_out vga_out
|
||||
(
|
||||
.clk(clk_vid),
|
||||
.ypbpr_en(ypbpr_en),
|
||||
.hsync(vga_hs_osd),
|
||||
.vsync(vga_vs_osd),
|
||||
.csync(vga_cs_osd),
|
||||
.dout(vga_o_t),
|
||||
.din(vga_data_osd),
|
||||
.hsync_o(vga_hs_t),
|
||||
.vsync_o(vga_vs_t),
|
||||
.csync_o(vga_cs_t)
|
||||
);
|
||||
|
||||
`ifndef MISTER_DISABLE_YC
|
||||
reg pal_en;
|
||||
reg yc_en;
|
||||
@ -1371,7 +1396,7 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
|
||||
reg [16:0] ColorBurst_Range;
|
||||
reg [39:0] PhaseInc;
|
||||
wire [23:0] yc_o;
|
||||
wire yc_hs, yc_vs, yc_cs;
|
||||
wire yc_hs, yc_vs, yc_cs, yc_de;
|
||||
|
||||
yc_out yc_out
|
||||
(
|
||||
@ -1383,25 +1408,78 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
|
||||
.hsync(vga_hs_osd),
|
||||
.vsync(vga_vs_osd),
|
||||
.csync(vga_cs_osd),
|
||||
.de(vga_de_osd),
|
||||
.dout(yc_o),
|
||||
.din(vga_data_osd),
|
||||
.hsync_o(yc_hs),
|
||||
.vsync_o(yc_vs),
|
||||
.csync_o(yc_cs)
|
||||
.csync_o(yc_cs),
|
||||
.de_o(yc_de)
|
||||
);
|
||||
|
||||
assign {vga_o, vga_hs, vga_vs, vga_cs } = ~yc_en ? {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t } : {yc_o, yc_hs, yc_vs, yc_cs };
|
||||
`else
|
||||
assign {vga_o, vga_hs, vga_vs, vga_cs } = {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t } ;
|
||||
`endif
|
||||
|
||||
wire cs1 = (vga_fb | vga_scaler) ? vgas_cs : vga_cs;
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire VGA_DISABLE;
|
||||
wire [23:0] vgas_o;
|
||||
wire vgas_hs, vgas_vs, vgas_cs, vgas_de;
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
vga_out vga_scaler_out
|
||||
(
|
||||
.clk(clk_hdmi),
|
||||
.ypbpr_en(ypbpr_en),
|
||||
.hsync(hdmi_hs_osd),
|
||||
.vsync(hdmi_vs_osd),
|
||||
.csync(hdmi_cs_osd),
|
||||
.de(hdmi_de_osd),
|
||||
.dout(vgas_o),
|
||||
.din({24{hdmi_de_osd}} & hdmi_data_osd),
|
||||
.hsync_o(vgas_hs),
|
||||
.vsync_o(vgas_vs),
|
||||
.csync_o(vgas_cs),
|
||||
.de_o(vgas_de)
|
||||
);
|
||||
`else
|
||||
assign {vgas_o, vgas_hs, vgas_vs, vgas_cs, vgas_de} = 0;
|
||||
`endif
|
||||
|
||||
assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ : (((vga_fb | vga_scaler) ? (~vgas_vs ^ VS[12]) : VGA_DISABLE ? 1'd1 : ~vga_vs) | csync_en);
|
||||
assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ : ((vga_fb | vga_scaler) ? ((csync_en ? ~vgas_cs : ~vgas_hs) ^ HS[12]) : VGA_DISABLE ? 1'd1 : (csync_en ? ~vga_cs : ~vga_hs));
|
||||
assign VGA_R = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[23:18] : VGA_DISABLE ? 6'd0 : vga_o[23:18];
|
||||
assign VGA_G = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[15:10] : VGA_DISABLE ? 6'd0 : vga_o[15:10];
|
||||
assign VGA_B = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[7:2] : VGA_DISABLE ? 6'd0 : vga_o[7:2] ;
|
||||
wire [23:0] vga_o, vga_o_t;
|
||||
wire vga_hs, vga_vs, vga_cs, vga_de, vga_hs_t, vga_vs_t, vga_cs_t, vga_de_t;
|
||||
vga_out vga_out
|
||||
(
|
||||
.clk(clk_vid),
|
||||
.ypbpr_en(ypbpr_en),
|
||||
.hsync(vga_hs_osd),
|
||||
.vsync(vga_vs_osd),
|
||||
.csync(vga_cs_osd),
|
||||
.de(vga_de_osd),
|
||||
.dout(vga_o_t),
|
||||
.din(vga_data_osd),
|
||||
.hsync_o(vga_hs_t),
|
||||
.vsync_o(vga_vs_t),
|
||||
.csync_o(vga_cs_t),
|
||||
.de_o(vga_de_t)
|
||||
);
|
||||
|
||||
`ifndef MISTER_DISABLE_YC
|
||||
assign {vga_o, vga_hs, vga_vs, vga_cs, vga_de } = ~yc_en ? {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t, vga_de_t } : {yc_o, yc_hs, yc_vs, yc_cs, yc_de };
|
||||
`else
|
||||
assign {vga_o, vga_hs, vga_vs, vga_cs, vga_de } = {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t, vga_de_t } ;
|
||||
`endif
|
||||
|
||||
wire vgas_en = vga_fb | vga_scaler;
|
||||
|
||||
wire cs1 = vgas_en ? vgas_cs : vga_cs;
|
||||
wire de1 = vgas_en ? vgas_de : vga_de;
|
||||
|
||||
assign VGA_VS = av_dis ? 1'bZ : ((vgas_en ? (~vgas_vs ^ VS[12]) : VGA_DISABLE ? 1'd1 : ~vga_vs) | csync_en);
|
||||
assign VGA_HS = av_dis ? 1'bZ : (vgas_en ? ((csync_en ? ~vgas_cs : ~vgas_hs) ^ HS[12]) : VGA_DISABLE ? 1'd1 : (csync_en ? ~vga_cs : ~vga_hs));
|
||||
assign VGA_R = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[23:18] : VGA_DISABLE ? 6'd0 : vga_o[23:18];
|
||||
assign VGA_G = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[15:10] : VGA_DISABLE ? 6'd0 : vga_o[15:10];
|
||||
assign VGA_B = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[7:2] : VGA_DISABLE ? 6'd0 : vga_o[7:2] ;
|
||||
|
||||
wire [1:0] vga_r = vgas_en ? vgas_o[17:16] : VGA_DISABLE ? 2'd0 : vga_o[17:16];
|
||||
wire [1:0] vga_g = vgas_en ? vgas_o[9:8] : VGA_DISABLE ? 2'd0 : vga_o[9:8];
|
||||
wire [1:0] vga_b = vgas_en ? vgas_o[1:0] : VGA_DISABLE ? 2'd0 : vga_o[1:0];
|
||||
`endif
|
||||
|
||||
reg video_sync = 0;
|
||||
@ -1431,14 +1509,14 @@ end
|
||||
|
||||
///////////////////////// Audio output ////////////////////////////////
|
||||
|
||||
assign SDCD_SPDIF =(SW[3] & ~spdif) ? 1'b0 : 1'bZ;
|
||||
assign SDCD_SPDIF = (mcp_en & ~spdif) ? 1'b0 : 1'bZ;
|
||||
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire analog_l, analog_r;
|
||||
|
||||
assign AUDIO_SPDIF = SW[3] ? 1'bZ : SW[0] ? HDMI_LRCLK : spdif;
|
||||
assign AUDIO_R = SW[3] ? 1'bZ : SW[0] ? HDMI_I2S : analog_r;
|
||||
assign AUDIO_L = SW[3] ? 1'bZ : SW[0] ? HDMI_SCLK : analog_l;
|
||||
assign AUDIO_SPDIF = av_dis ? 1'bZ : (SW[0] | mcp_en) ? HDMI_LRCLK : spdif;
|
||||
assign AUDIO_R = av_dis ? 1'bZ : (SW[0] | mcp_en) ? HDMI_I2S : analog_r;
|
||||
assign AUDIO_L = av_dis ? 1'bZ : (SW[0] | mcp_en) ? HDMI_SCLK : analog_l;
|
||||
`endif
|
||||
|
||||
assign HDMI_MCLK = clk_audio;
|
||||
@ -1491,27 +1569,27 @@ audio_out audio_out
|
||||
|
||||
|
||||
`ifndef MISTER_DISABLE_ALSA
|
||||
wire aspi_sck,aspi_mosi,aspi_ss,aspi_miso;
|
||||
cyclonev_hps_interface_peripheral_spi_master spi
|
||||
(
|
||||
wire aspi_sck,aspi_mosi,aspi_ss,aspi_miso;
|
||||
cyclonev_hps_interface_peripheral_spi_master spi
|
||||
(
|
||||
.sclk_out(aspi_sck),
|
||||
.txd(aspi_mosi), // mosi
|
||||
.rxd(aspi_miso), // miso
|
||||
|
||||
.ss_0_n(aspi_ss),
|
||||
.ss_in_n(1)
|
||||
);
|
||||
);
|
||||
|
||||
wire [28:0] alsa_address;
|
||||
wire [63:0] alsa_readdata;
|
||||
wire alsa_ready;
|
||||
wire alsa_req;
|
||||
wire alsa_late;
|
||||
wire [28:0] alsa_address;
|
||||
wire [63:0] alsa_readdata;
|
||||
wire alsa_ready;
|
||||
wire alsa_req;
|
||||
wire alsa_late;
|
||||
|
||||
wire [15:0] alsa_l, alsa_r;
|
||||
wire [15:0] alsa_l, alsa_r;
|
||||
|
||||
alsa alsa
|
||||
(
|
||||
alsa alsa
|
||||
(
|
||||
.reset(reset),
|
||||
.clk(clk_audio),
|
||||
|
||||
@ -1527,7 +1605,7 @@ alsa alsa
|
||||
|
||||
.pcm_l(alsa_l),
|
||||
.pcm_r(alsa_r)
|
||||
);
|
||||
);
|
||||
`endif
|
||||
|
||||
//////////////// User I/O (USB 3.0 connector) /////////////////////////
|
||||
@ -1728,7 +1806,7 @@ emu emu
|
||||
.SDRAM2_nRAS(SDRAM2_nRAS),
|
||||
.SDRAM2_nCAS(SDRAM2_nCAS),
|
||||
.SDRAM2_CLK(SDRAM2_CLK),
|
||||
.SDRAM2_EN(SW[3]),
|
||||
.SDRAM2_EN(io_dig),
|
||||
`endif
|
||||
|
||||
.BUTTONS(btn),
|
||||
@ -1738,11 +1816,7 @@ emu emu
|
||||
.SD_MOSI(SD_MOSI),
|
||||
.SD_MISO(SD_MISO),
|
||||
.SD_CS(SD_CS),
|
||||
`ifdef MISTER_DUAL_SDRAM
|
||||
.SD_CD(mcp_sdcd),
|
||||
`else
|
||||
.SD_CD(mcp_sdcd & (SW[0] ? VGA_HS : (SW[3] | SDCD_SPDIF))),
|
||||
`endif
|
||||
.SD_CD(SD_CD),
|
||||
|
||||
.UART_CTS(uart_rts),
|
||||
.UART_RTS(uart_cts),
|
||||
@ -1771,19 +1845,17 @@ assign sync_out = sync_in ^ pol;
|
||||
|
||||
reg pol;
|
||||
always @(posedge clk) begin
|
||||
integer pos = 0, neg = 0, cnt = 0;
|
||||
reg [31:0] cnt;
|
||||
reg s1,s2;
|
||||
|
||||
s1 <= sync_in;
|
||||
s2 <= s1;
|
||||
cnt <= s2 ? (cnt - 1) : (cnt + 1);
|
||||
|
||||
if(~s2 & s1) neg <= cnt;
|
||||
if(s2 & ~s1) pos <= cnt;
|
||||
|
||||
cnt <= cnt + 1;
|
||||
if(s2 != s1) cnt <= 0;
|
||||
|
||||
pol <= pos > neg;
|
||||
if(~s2 & s1) begin
|
||||
cnt <= 0;
|
||||
pol <= cnt[31];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -7,13 +7,15 @@ module vga_out
|
||||
input hsync,
|
||||
input vsync,
|
||||
input csync,
|
||||
input de,
|
||||
|
||||
input [23:0] din,
|
||||
output [23:0] dout,
|
||||
|
||||
output reg hsync_o,
|
||||
output reg vsync_o,
|
||||
output reg csync_o
|
||||
output reg csync_o,
|
||||
output reg de_o
|
||||
);
|
||||
|
||||
wire [7:0] red = din[23:16];
|
||||
@ -35,8 +37,8 @@ always @(posedge clk) begin
|
||||
reg [18:0] y_1b, pb_1b, pr_1b;
|
||||
reg [18:0] y_2, pb_2, pr_2;
|
||||
reg [23:0] din1, din2;
|
||||
reg hsync2, vsync2, csync2;
|
||||
reg hsync1, vsync1, csync1;
|
||||
reg hsync2, vsync2, csync2, de2;
|
||||
reg hsync1, vsync1, csync1, de1;
|
||||
|
||||
y_1r <= {red, 6'd0} + {red, 3'd0} + {red, 2'd0} + red;
|
||||
pb_1r <= 19'd32768 - ({red, 5'd0} + {red, 3'd0} + {red, 1'd0});
|
||||
@ -61,6 +63,7 @@ always @(posedge clk) begin
|
||||
hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync;
|
||||
vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync;
|
||||
csync_o <= csync2; csync2 <= csync1; csync1 <= csync;
|
||||
de_o <= de2; de2 <= de1; de1 <= de;
|
||||
|
||||
rgb <= din2; din2 <= din1; din1 <= din;
|
||||
end
|
||||
|
||||
@ -170,10 +170,8 @@ reg [11:0] mul_arg1, mul_arg2;
|
||||
wire [23:0] mul_res;
|
||||
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);
|
||||
|
||||
wire [11:0] wideres = mul_res[11:0] + hsize;
|
||||
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg [11:0] oheight,htarget,wres;
|
||||
reg [11:0] oheight,htarget,wres,hinteger,wideres;
|
||||
reg [12:0] arxf,aryf;
|
||||
reg [3:0] cnt;
|
||||
reg narrow;
|
||||
@ -264,7 +262,8 @@ always @(posedge CLK_VIDEO) begin
|
||||
// [3] 1080 / 512 * 512 * 4 / 3 / 512 * 512 -> 1024
|
||||
|
||||
7: if(mul_res <= HDMI_WIDTH) begin
|
||||
cnt <= 10;
|
||||
hinteger = mul_res[11:0];
|
||||
cnt <= 12;
|
||||
end
|
||||
|
||||
8: begin
|
||||
@ -286,8 +285,20 @@ always @(posedge CLK_VIDEO) begin
|
||||
// [3] 1920 / 512 * 512 -> 1536
|
||||
|
||||
10: begin
|
||||
narrow <= ((htarget - mul_res[11:0]) <= (wideres - htarget)) || (wideres > HDMI_WIDTH);
|
||||
wres <= mul_res[11:0] == htarget ? mul_res[11:0] : wideres;
|
||||
hinteger <= mul_res[11:0];
|
||||
mul_arg1 <= vsize;
|
||||
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
|
||||
mul_start <= 1;
|
||||
end
|
||||
|
||||
11: begin
|
||||
oheight <= mul_res[11:0];
|
||||
end
|
||||
|
||||
12: begin
|
||||
wideres <= hinteger + hsize;
|
||||
narrow <= ((htarget - hinteger) <= (wideres - htarget)) || (wideres > HDMI_WIDTH);
|
||||
wres <= hinteger == htarget ? hinteger : wideres;
|
||||
end
|
||||
// [1] 1066 - 720 = 346 <= 1440 - 1066 = 374 || 1440 > 1920 -> true
|
||||
// [2] 1280 - 1280 = 0 <= 1920 - 1280 = 640 || 1920 > 1920 -> true
|
||||
@ -299,11 +310,11 @@ always @(posedge CLK_VIDEO) begin
|
||||
// to target width, meaning it is not optimal for source aspect ratio.
|
||||
// otherwise it is set to narrow width that is optimal.
|
||||
|
||||
11: begin
|
||||
13: begin
|
||||
case(SCALE)
|
||||
2: arxf <= {1'b1, mul_res[11:0]};
|
||||
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? mul_res[11:0] : wres};
|
||||
4: arxf <= {1'b1, narrow ? mul_res[11:0] : wres};
|
||||
2: arxf <= {1'b1, hinteger};
|
||||
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? hinteger : wres};
|
||||
4: arxf <= {1'b1, narrow ? hinteger : wres};
|
||||
default: arxf <= {1'b1, div_num[11:0]};
|
||||
endcase
|
||||
aryf <= {1'b1, oheight};
|
||||
|
||||
@ -36,13 +36,15 @@ module yc_out
|
||||
input hsync,
|
||||
input vsync,
|
||||
input csync,
|
||||
input de,
|
||||
|
||||
input [23:0] din,
|
||||
output [23:0] dout,
|
||||
|
||||
output reg hsync_o,
|
||||
output reg vsync_o,
|
||||
output reg csync_o
|
||||
output reg csync_o,
|
||||
output reg de_o
|
||||
);
|
||||
|
||||
wire [7:0] red = din[23:16];
|
||||
@ -61,6 +63,7 @@ typedef struct {
|
||||
logic hsync;
|
||||
logic vsync;
|
||||
logic csync;
|
||||
logic de;
|
||||
} phase_t;
|
||||
|
||||
localparam MAX_PHASES = 7'd8;
|
||||
@ -211,11 +214,11 @@ always_ff @(posedge clk) begin
|
||||
end
|
||||
|
||||
// Adjust sync timing correctly
|
||||
phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync;
|
||||
phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync;
|
||||
phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync;
|
||||
phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync;
|
||||
hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync;
|
||||
phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync; phase[1].de <= de;
|
||||
phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync; phase[2].de <= phase[1].de;
|
||||
phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync; phase[3].de <= phase[2].de;
|
||||
phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync; phase[4].de <= phase[3].de;
|
||||
hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync; de_o <= phase[4].de;
|
||||
|
||||
phase[1].y <= phase[0].y; phase[2].y <= phase[1].y; phase[3].y <= phase[2].y; phase[4].y <= phase[3].y; phase[5].y <= phase[4].y;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user