mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 23:01:37 +03:00
Update sys.
This commit is contained in:
@ -226,7 +226,7 @@ video_calc video_calc
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.new_vmode(new_vmode),
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.new_vmode(new_vmode),
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.video_rotated(video_rotated),
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.video_rotated(video_rotated),
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.par_num(byte_cnt[3:0]),
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.par_num(byte_cnt[4:0]),
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.dout(vc_dout)
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.dout(vc_dout)
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);
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);
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@ -502,7 +502,7 @@ always@(posedge clk_sys) begin : uio_block
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'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
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'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
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//Video res.
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//Video res.
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'h23: if(!byte_cnt[MAX_W:4]) io_dout <= vc_dout;
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'h23: if(!byte_cnt[MAX_W:5]) io_dout <= vc_dout;
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//RTC
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//RTC
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'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
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'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
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@ -872,7 +872,7 @@ module video_calc
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input new_vmode,
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input new_vmode,
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input video_rotated,
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input video_rotated,
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input [3:0] par_num,
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input [4:0] par_num,
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output reg [15:0] dout
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output reg [15:0] dout
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);
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);
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@ -893,6 +893,9 @@ always @(posedge clk_sys) begin
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13: dout <= vid_vtime_hdmi[31:16];
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13: dout <= vid_vtime_hdmi[31:16];
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14: dout <= vid_ccnt[15:0];
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14: dout <= vid_ccnt[15:0];
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15: dout <= vid_ccnt[31:16];
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15: dout <= vid_ccnt[31:16];
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16: dout <= vid_pixrep;
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17: dout <= vid_de_h;
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18: dout <= vid_de_v;
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default dout <= 0;
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default dout <= 0;
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endcase
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endcase
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end
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end
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@ -902,24 +905,44 @@ reg [31:0] vid_vcnt = 0;
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reg [31:0] vid_ccnt = 0;
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reg [31:0] vid_ccnt = 0;
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reg [7:0] vid_nres = 0;
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reg [7:0] vid_nres = 0;
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reg [1:0] vid_int = 0;
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reg [1:0] vid_int = 0;
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reg [7:0] vid_pixrep;
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reg [15:0] vid_de_h;
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reg [7:0] vid_de_v;
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always @(posedge clk_vid) begin
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always @(posedge clk_vid) begin
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integer hcnt;
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integer hcnt;
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integer vcnt;
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integer vcnt;
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integer ccnt;
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integer ccnt;
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reg old_vs= 0, old_de = 0, old_vmode = 0;
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reg [7:0] pcnt;
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reg [7:0] de_v;
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reg [15:0] de_h;
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reg old_vs = 0, old_hs = 0, old_hs_vclk = 0, old_de = 0, old_de_vclk = 0, old_de1 = 0, old_vmode = 0;
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reg [3:0] resto = 0;
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reg [3:0] resto = 0;
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reg calch = 0;
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reg calch = 0;
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if(calch & de) ccnt <= ccnt + 1;
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if(calch & de) ccnt <= ccnt + 1;
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pcnt <= pcnt + 1'd1;
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old_hs_vclk <= hs;
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de_h <= de_h + 1'd1;
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if(old_hs_vclk & ~hs) de_h <= 1;
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old_de_vclk <= de;
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if(calch & ~old_de_vclk & de) vid_de_h <= de_h;
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if(ce_pix) begin
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if(ce_pix) begin
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old_vs <= vs;
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old_vs <= vs;
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old_hs <= hs;
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old_de <= de;
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old_de <= de;
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old_de1 <= old_de;
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pcnt <= 1;
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if(~vs & ~old_de & de) vcnt <= vcnt + 1;
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if(~vs & ~old_de & de) vcnt <= vcnt + 1;
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if(calch & de) hcnt <= hcnt + 1;
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if(calch & de) hcnt <= hcnt + 1;
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if(old_de & ~de) calch <= 0;
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if(old_de & ~de) calch <= 0;
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if(~old_de1 & old_de) vid_pixrep <= pcnt;
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if(old_hs & ~hs) de_v <= de_v + 1'd1;
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if(calch & ~old_de & de) vid_de_v <= de_v;
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if(old_vs & ~vs) begin
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if(old_vs & ~vs) begin
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vid_int <= {vid_int[0],f1};
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vid_int <= {vid_int[0],f1};
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@ -939,6 +962,7 @@ always @(posedge clk_vid) begin
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hcnt <= 0;
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hcnt <= 0;
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ccnt <= 0;
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ccnt <= 0;
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calch <= 1;
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calch <= 1;
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de_v <= 0;
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end
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end
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end
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end
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end
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end
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@ -8,10 +8,12 @@ module mcp23009
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output reg [2:0] btn,
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output reg [2:0] btn,
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input [2:0] led,
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input [2:0] led,
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output reg sd_cd,
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output reg flg_sd_cd,
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output reg flg_present,
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output reg flg_mode,
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output scl,
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output scl,
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inout sda
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inout sda
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);
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);
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@ -50,7 +52,9 @@ always@(posedge clk) begin
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idx <= 0;
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idx <= 0;
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btn <= 0;
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btn <= 0;
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rw <= 0;
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rw <= 0;
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sd_cd <= 1;
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flg_sd_cd <= 1;
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flg_present <= 0;
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flg_mode <= 1;
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end
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end
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else begin
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else begin
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if(~&init_data[idx]) begin
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if(~&init_data[idx]) begin
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@ -84,7 +88,10 @@ always@(posedge clk) begin
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state <= 0;
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state <= 0;
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rw <= 0;
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rw <= 0;
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if(!error) begin
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if(!error) begin
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if(rw) {sd_cd, btn} <= {dout[7], dout[5:3]};
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if(rw) begin
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{flg_sd_cd, flg_mode, btn} <= {dout[7:3]};
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flg_present <= 1;
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end
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rw <= ~rw;
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rw <= ~rw;
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end
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end
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end
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end
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@ -1,44 +1,5 @@
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"
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set_global_assignment -library "pll_cfg" -name MISC_FILE [file join $::quartus(qip_path) "pll_cfg.cmp"]
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_QSYS_MODE "UNKNOWN"
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set_global_assignment -name SYNTHESIS_ONLY_QIP ON
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set_global_assignment -name SYNTHESIS_ONLY_QIP ON
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_NAME "cGxsX2hkbWlfY2Zn"
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set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg.v"]
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
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set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg_hdmi.v"]
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
|
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||||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ=="
|
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc="
|
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
|
|
||||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
|
|
||||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
|
|
||||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
|
|
||||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
|
|
||||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
|
|
||||||
|
|
||||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg.v"]
|
|
||||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_top.v"]
|
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_top.v"]
|
||||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_core.v"]
|
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_core.v"]
|
||||||
|
|
||||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
|
|
||||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
|
|
||||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"
|
|
||||||
|
@ -16,7 +16,7 @@
|
|||||||
module altera_pll_reconfig_core
|
module altera_pll_reconfig_core
|
||||||
#(
|
#(
|
||||||
parameter reconf_width = 64,
|
parameter reconf_width = 64,
|
||||||
parameter device_family = "Stratix V",
|
parameter device_family = "Cyclone V",
|
||||||
// MIF Streaming parameters
|
// MIF Streaming parameters
|
||||||
parameter RECONFIG_ADDR_WIDTH = 6,
|
parameter RECONFIG_ADDR_WIDTH = 6,
|
||||||
parameter RECONFIG_DATA_WIDTH = 32,
|
parameter RECONFIG_DATA_WIDTH = 32,
|
||||||
@ -1883,7 +1883,7 @@ module fpll_dprio_init (
|
|||||||
endmodule
|
endmodule
|
||||||
module dyn_phase_shift
|
module dyn_phase_shift
|
||||||
#(
|
#(
|
||||||
parameter device_family = "Stratix V"
|
parameter device_family = "Cyclone V"
|
||||||
) (
|
) (
|
||||||
|
|
||||||
input wire clk,
|
input wire clk,
|
||||||
@ -2112,7 +2112,7 @@ endmodule
|
|||||||
module generic_lcell_comb
|
module generic_lcell_comb
|
||||||
#(
|
#(
|
||||||
//parameter
|
//parameter
|
||||||
parameter family = "Stratix V",
|
parameter family = "Cyclone V",
|
||||||
parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
|
parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
|
||||||
parameter dont_touch = "on"
|
parameter dont_touch = "on"
|
||||||
) (
|
) (
|
||||||
|
@ -16,7 +16,7 @@
|
|||||||
module altera_pll_reconfig_top
|
module altera_pll_reconfig_top
|
||||||
#(
|
#(
|
||||||
parameter reconf_width = 64,
|
parameter reconf_width = 64,
|
||||||
parameter device_family = "Stratix V",
|
parameter device_family = "Cyclone V",
|
||||||
parameter RECONFIG_ADDR_WIDTH = 6,
|
parameter RECONFIG_ADDR_WIDTH = 6,
|
||||||
parameter RECONFIG_DATA_WIDTH = 32,
|
parameter RECONFIG_DATA_WIDTH = 32,
|
||||||
|
|
||||||
|
1282
sys/pll_cfg/pll_cfg_hdmi.v
Normal file
1282
sys/pll_cfg/pll_cfg_hdmi.v
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,4 @@
|
|||||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ]
|
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ]
|
||||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ]
|
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ]
|
||||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ]
|
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ]
|
||||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ]
|
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ]
|
||||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ]
|
|
||||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ]
|
|
||||||
|
@ -16,13 +16,6 @@ set_location_assignment PIN_V10 -to ADC_SCK
|
|||||||
set_location_assignment PIN_AC4 -to ADC_SDI
|
set_location_assignment PIN_AC4 -to ADC_SDI
|
||||||
set_location_assignment PIN_AD4 -to ADC_SDO
|
set_location_assignment PIN_AD4 -to ADC_SDO
|
||||||
|
|
||||||
#============================================================
|
|
||||||
# ARDUINO
|
|
||||||
#============================================================
|
|
||||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
|
|
||||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
|
|
||||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
|
|
||||||
|
|
||||||
#============================================================
|
#============================================================
|
||||||
# I2C LEDS/BUTTONS
|
# I2C LEDS/BUTTONS
|
||||||
#============================================================
|
#============================================================
|
||||||
|
@ -25,6 +25,7 @@ set_false_path -from [get_ports {KEY*}]
|
|||||||
set_false_path -from [get_ports {BTN_*}]
|
set_false_path -from [get_ports {BTN_*}]
|
||||||
set_false_path -to [get_ports {LED_*}]
|
set_false_path -to [get_ports {LED_*}]
|
||||||
set_false_path -to [get_ports {VGA_*}]
|
set_false_path -to [get_ports {VGA_*}]
|
||||||
|
set_false_path -from [get_ports {VGA_EN}]
|
||||||
set_false_path -to [get_ports {AUDIO_SPDIF}]
|
set_false_path -to [get_ports {AUDIO_SPDIF}]
|
||||||
set_false_path -to [get_ports {AUDIO_L}]
|
set_false_path -to [get_ports {AUDIO_L}]
|
||||||
set_false_path -to [get_ports {AUDIO_R}]
|
set_false_path -to [get_ports {AUDIO_R}]
|
||||||
@ -34,6 +35,7 @@ set_false_path -from {cfg[*]}
|
|||||||
set_false_path -from {VSET[*]}
|
set_false_path -from {VSET[*]}
|
||||||
set_false_path -to {wcalc[*] hcalc[*]}
|
set_false_path -to {wcalc[*] hcalc[*]}
|
||||||
set_false_path -to {hdmi_width[*] hdmi_height[*]}
|
set_false_path -to {hdmi_width[*] hdmi_height[*]}
|
||||||
|
set_false_path -to {deb_* btn_en btn_up}
|
||||||
|
|
||||||
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
|
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
|
||||||
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
|
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
|
||||||
@ -58,6 +60,7 @@ set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
|
|||||||
set_false_path -from {aflt_* acx* acy* areset* arc*}
|
set_false_path -from {aflt_* acx* acy* areset* arc*}
|
||||||
set_false_path -from {arx* ary*}
|
set_false_path -from {arx* ary*}
|
||||||
set_false_path -from {vs_line*}
|
set_false_path -from {vs_line*}
|
||||||
|
set_false_path -from {ColorBurst_Range* PhaseInc* pal_en cvbs yc_en}
|
||||||
|
|
||||||
set_false_path -from {ascal|o_ihsize*}
|
set_false_path -from {ascal|o_ihsize*}
|
||||||
set_false_path -from {ascal|o_ivsize*}
|
set_false_path -from {ascal|o_ivsize*}
|
||||||
@ -70,4 +73,5 @@ set_false_path -from {ascal|o_htotal* ascal|o_vtotal*}
|
|||||||
set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*}
|
set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*}
|
||||||
set_false_path -from {ascal|o_hsize* ascal|o_vsize*}
|
set_false_path -from {ascal|o_hsize* ascal|o_vsize*}
|
||||||
|
|
||||||
set_false_path -from {mcp23009|sd_cd}
|
set_false_path -from {mcp23009|flg_*}
|
||||||
|
set_false_path -to {sysmem|fpga_interfaces|clocks_resets*}
|
||||||
|
882
sys/sys_top.v
882
sys/sys_top.v
File diff suppressed because it is too large
Load Diff
@ -7,13 +7,15 @@ module vga_out
|
|||||||
input hsync,
|
input hsync,
|
||||||
input vsync,
|
input vsync,
|
||||||
input csync,
|
input csync,
|
||||||
|
input de,
|
||||||
|
|
||||||
input [23:0] din,
|
input [23:0] din,
|
||||||
output [23:0] dout,
|
output [23:0] dout,
|
||||||
|
|
||||||
output reg hsync_o,
|
output reg hsync_o,
|
||||||
output reg vsync_o,
|
output reg vsync_o,
|
||||||
output reg csync_o
|
output reg csync_o,
|
||||||
|
output reg de_o
|
||||||
);
|
);
|
||||||
|
|
||||||
wire [7:0] red = din[23:16];
|
wire [7:0] red = din[23:16];
|
||||||
@ -35,8 +37,8 @@ always @(posedge clk) begin
|
|||||||
reg [18:0] y_1b, pb_1b, pr_1b;
|
reg [18:0] y_1b, pb_1b, pr_1b;
|
||||||
reg [18:0] y_2, pb_2, pr_2;
|
reg [18:0] y_2, pb_2, pr_2;
|
||||||
reg [23:0] din1, din2;
|
reg [23:0] din1, din2;
|
||||||
reg hsync2, vsync2, csync2;
|
reg hsync2, vsync2, csync2, de2;
|
||||||
reg hsync1, vsync1, csync1;
|
reg hsync1, vsync1, csync1, de1;
|
||||||
|
|
||||||
y_1r <= {red, 6'd0} + {red, 3'd0} + {red, 2'd0} + red;
|
y_1r <= {red, 6'd0} + {red, 3'd0} + {red, 2'd0} + red;
|
||||||
pb_1r <= 19'd32768 - ({red, 5'd0} + {red, 3'd0} + {red, 1'd0});
|
pb_1r <= 19'd32768 - ({red, 5'd0} + {red, 3'd0} + {red, 1'd0});
|
||||||
@ -61,6 +63,7 @@ always @(posedge clk) begin
|
|||||||
hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync;
|
hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync;
|
||||||
vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync;
|
vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync;
|
||||||
csync_o <= csync2; csync2 <= csync1; csync1 <= csync;
|
csync_o <= csync2; csync2 <= csync1; csync1 <= csync;
|
||||||
|
de_o <= de2; de2 <= de1; de1 <= de;
|
||||||
|
|
||||||
rgb <= din2; din2 <= din1; din1 <= din;
|
rgb <= din2; din2 <= din1; din1 <= din;
|
||||||
end
|
end
|
||||||
|
@ -170,10 +170,8 @@ reg [11:0] mul_arg1, mul_arg2;
|
|||||||
wire [23:0] mul_res;
|
wire [23:0] mul_res;
|
||||||
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);
|
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);
|
||||||
|
|
||||||
wire [11:0] wideres = mul_res[11:0] + hsize;
|
|
||||||
|
|
||||||
always @(posedge CLK_VIDEO) begin
|
always @(posedge CLK_VIDEO) begin
|
||||||
reg [11:0] oheight,htarget,wres;
|
reg [11:0] oheight,htarget,wres,hinteger,wideres;
|
||||||
reg [12:0] arxf,aryf;
|
reg [12:0] arxf,aryf;
|
||||||
reg [3:0] cnt;
|
reg [3:0] cnt;
|
||||||
reg narrow;
|
reg narrow;
|
||||||
@ -264,7 +262,8 @@ always @(posedge CLK_VIDEO) begin
|
|||||||
// [3] 1080 / 512 * 512 * 4 / 3 / 512 * 512 -> 1024
|
// [3] 1080 / 512 * 512 * 4 / 3 / 512 * 512 -> 1024
|
||||||
|
|
||||||
7: if(mul_res <= HDMI_WIDTH) begin
|
7: if(mul_res <= HDMI_WIDTH) begin
|
||||||
cnt <= 10;
|
hinteger = mul_res[11:0];
|
||||||
|
cnt <= 12;
|
||||||
end
|
end
|
||||||
|
|
||||||
8: begin
|
8: begin
|
||||||
@ -285,9 +284,21 @@ always @(posedge CLK_VIDEO) begin
|
|||||||
// [2] 1920 / 640 * 640 -> 1920
|
// [2] 1920 / 640 * 640 -> 1920
|
||||||
// [3] 1920 / 512 * 512 -> 1536
|
// [3] 1920 / 512 * 512 -> 1536
|
||||||
|
|
||||||
10: begin
|
10: begin
|
||||||
narrow <= ((htarget - mul_res[11:0]) <= (wideres - htarget)) || (wideres > HDMI_WIDTH);
|
hinteger <= mul_res[11:0];
|
||||||
wres <= mul_res[11:0] == htarget ? mul_res[11:0] : wideres;
|
mul_arg1 <= vsize;
|
||||||
|
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
|
||||||
|
mul_start <= 1;
|
||||||
|
end
|
||||||
|
|
||||||
|
11: begin
|
||||||
|
oheight <= mul_res[11:0];
|
||||||
|
end
|
||||||
|
|
||||||
|
12: begin
|
||||||
|
wideres <= hinteger + hsize;
|
||||||
|
narrow <= ((htarget - hinteger) <= (wideres - htarget)) || (wideres > HDMI_WIDTH);
|
||||||
|
wres <= hinteger == htarget ? hinteger : wideres;
|
||||||
end
|
end
|
||||||
// [1] 1066 - 720 = 346 <= 1440 - 1066 = 374 || 1440 > 1920 -> true
|
// [1] 1066 - 720 = 346 <= 1440 - 1066 = 374 || 1440 > 1920 -> true
|
||||||
// [2] 1280 - 1280 = 0 <= 1920 - 1280 = 640 || 1920 > 1920 -> true
|
// [2] 1280 - 1280 = 0 <= 1920 - 1280 = 640 || 1920 > 1920 -> true
|
||||||
@ -299,11 +310,11 @@ always @(posedge CLK_VIDEO) begin
|
|||||||
// to target width, meaning it is not optimal for source aspect ratio.
|
// to target width, meaning it is not optimal for source aspect ratio.
|
||||||
// otherwise it is set to narrow width that is optimal.
|
// otherwise it is set to narrow width that is optimal.
|
||||||
|
|
||||||
11: begin
|
13: begin
|
||||||
case(SCALE)
|
case(SCALE)
|
||||||
2: arxf <= {1'b1, mul_res[11:0]};
|
2: arxf <= {1'b1, hinteger};
|
||||||
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? mul_res[11:0] : wres};
|
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? hinteger : wres};
|
||||||
4: arxf <= {1'b1, narrow ? mul_res[11:0] : wres};
|
4: arxf <= {1'b1, narrow ? hinteger : wres};
|
||||||
default: arxf <= {1'b1, div_num[11:0]};
|
default: arxf <= {1'b1, div_num[11:0]};
|
||||||
endcase
|
endcase
|
||||||
aryf <= {1'b1, oheight};
|
aryf <= {1'b1, oheight};
|
||||||
|
@ -36,13 +36,15 @@ module yc_out
|
|||||||
input hsync,
|
input hsync,
|
||||||
input vsync,
|
input vsync,
|
||||||
input csync,
|
input csync,
|
||||||
|
input de,
|
||||||
|
|
||||||
input [23:0] din,
|
input [23:0] din,
|
||||||
output [23:0] dout,
|
output [23:0] dout,
|
||||||
|
|
||||||
output reg hsync_o,
|
output reg hsync_o,
|
||||||
output reg vsync_o,
|
output reg vsync_o,
|
||||||
output reg csync_o
|
output reg csync_o,
|
||||||
|
output reg de_o
|
||||||
);
|
);
|
||||||
|
|
||||||
wire [7:0] red = din[23:16];
|
wire [7:0] red = din[23:16];
|
||||||
@ -61,6 +63,7 @@ typedef struct {
|
|||||||
logic hsync;
|
logic hsync;
|
||||||
logic vsync;
|
logic vsync;
|
||||||
logic csync;
|
logic csync;
|
||||||
|
logic de;
|
||||||
} phase_t;
|
} phase_t;
|
||||||
|
|
||||||
localparam MAX_PHASES = 7'd8;
|
localparam MAX_PHASES = 7'd8;
|
||||||
@ -211,11 +214,11 @@ always_ff @(posedge clk) begin
|
|||||||
end
|
end
|
||||||
|
|
||||||
// Adjust sync timing correctly
|
// Adjust sync timing correctly
|
||||||
phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync;
|
phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync; phase[1].de <= de;
|
||||||
phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync;
|
phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync; phase[2].de <= phase[1].de;
|
||||||
phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync;
|
phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync; phase[3].de <= phase[2].de;
|
||||||
phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync;
|
phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync; phase[4].de <= phase[3].de;
|
||||||
hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync;
|
hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync; de_o <= phase[4].de;
|
||||||
|
|
||||||
phase[1].y <= phase[0].y; phase[2].y <= phase[1].y; phase[3].y <= phase[2].y; phase[4].y <= phase[3].y; phase[5].y <= phase[4].y;
|
phase[1].y <= phase[0].y; phase[2].y <= phase[1].y; phase[3].y <= phase[2].y; phase[4].y <= phase[3].y; phase[5].y <= phase[4].y;
|
||||||
|
|
||||||
|
Reference in New Issue
Block a user