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Update sys.

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This commit is contained in:
Sorgelig
2024-04-21 23:13:01 +08:00
parent 16b743e4bc
commit 5214a07dcf
14 changed files with 1848 additions and 490 deletions
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9
sys/vga_out.sv
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@ -7,13 +7,15 @@ module vga_out
input hsync,
input vsync,
input csync,
input de,
input [23:0] din,
output [23:0] dout,
output reg hsync_o,
output reg vsync_o,
output reg csync_o
output reg csync_o,
output reg de_o
);
wire [7:0] red = din[23:16];
@ -35,8 +37,8 @@ always @(posedge clk) begin
reg [18:0] y_1b, pb_1b, pr_1b;
reg [18:0] y_2, pb_2, pr_2;
reg [23:0] din1, din2;
reg hsync2, vsync2, csync2;
reg hsync1, vsync1, csync1;
reg hsync2, vsync2, csync2, de2;
reg hsync1, vsync1, csync1, de1;
y_1r <= {red, 6'd0} + {red, 3'd0} + {red, 2'd0} + red;
pb_1r <= 19'd32768 - ({red, 5'd0} + {red, 3'd0} + {red, 1'd0});
@ -61,6 +63,7 @@ always @(posedge clk) begin
hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync;
vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync;
csync_o <= csync2; csync2 <= csync1; csync1 <= csync;
de_o <= de2; de2 <= de1; de1 <= de;
rgb <= din2; din2 <= din1; din1 <= din;
end