Some cleanup.

TSConf-lite.qsf

@@ -393,7 +393,6 @@ set_global_assignment -name VERILOG_FILE src/video/mem/video_tmbuf.v
 set_global_assignment -name VERILOG_FILE src/video/mem/video_sfile.v
 set_global_assignment -name VERILOG_FILE src/video/mem/video_cram.v
 set_global_assignment -name VERILOG_FILE src/video/video_top.v
-set_global_assignment -name VHDL_FILE src/gen_rom.vhd
 set_global_assignment -name VHDL_FILE src/keyboard.vhd
 set_global_assignment -name VERILOG_FILE src/kempston_mouse.v
 set_global_assignment -name VERILOG_FILE src/spi.v

TSConf.qsf

@@ -399,7 +399,6 @@ set_global_assignment -name VERILOG_FILE src/video/mem/video_tmbuf.v
 set_global_assignment -name VERILOG_FILE src/video/mem/video_sfile.v
 set_global_assignment -name VERILOG_FILE src/video/mem/video_cram.v
 set_global_assignment -name VERILOG_FILE src/video/video_top.v
-set_global_assignment -name VHDL_FILE src/gen_rom.vhd
 set_global_assignment -name VHDL_FILE src/keyboard.vhd
 set_global_assignment -name VERILOG_FILE src/kempston_mouse.v
 set_global_assignment -name VERILOG_FILE src/spi.v

TSConf.sv

@@ -109,6 +109,7 @@ localparam CONF_STR = {
 	"TSConf;;",
 	"O5,Aspect ratio,4:3,16:9;",
 	"O12,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
+	"-;",
 	"O34,Stereo mix,None,25%,50%,100%;",
 	"OST,General Sound,512KB,1MB,2MB,4MB;",
 	"-;",

src/gen_rom.vhd

@@ -1,65 +0,0 @@
--- altera message_off 10306
-
-library ieee;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.ALL;
-use IEEE.numeric_std.all;
-
-entity gen_rom is
-
-	generic 
-	(
-		INIT_FILE  : string  := "";
-		ADDR_WIDTH : natural := 14;
-		DATA_WIDTH : natural := 8
-	);
-
-	port 
-	(
-		wrclock   : in  std_logic;
-		wraddress : in  std_logic_vector((ADDR_WIDTH - 1) downto 0) := (others => '0');
-		data	    : in  std_logic_vector((DATA_WIDTH - 1) downto 0) := (others => '0');
-		wren      : in  std_logic := '0';
-
-		rdclock   : in  std_logic;
-		rdaddress : in  std_logic_vector((ADDR_WIDTH - 1) downto 0);
-		q         : out std_logic_vector((DATA_WIDTH - 1) downto 0);
-		cs        : in  std_logic := '1'
-	);
-
-end gen_rom;
-
-architecture rtl of gen_rom is
-
-	subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
-	type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
-
-	shared variable ram : memory_t;
-	
-	attribute ram_init_file : string;
-	attribute ram_init_file of ram : variable is INIT_FILE;
-	
-	signal q0 : std_logic_vector((DATA_WIDTH - 1) downto 0);
-	
-
-begin
-
-	q<= q0 when cs = '1' else (others => '1');
-
-	-- WR Port
-	process(wrclock) begin
-		if(rising_edge(wrclock)) then 
-			if(wren = '1') then
-				ram(to_integer(unsigned(wraddress))) := data;
-			end if;
-		end if;
-	end process;
-
-	-- RD Port
-	process(rdclock) begin
-		if(rising_edge(rdclock)) then 
-			 q0 <= ram(to_integer(unsigned(rdaddress)));
-		end if;
-	end process;
-
-end rtl;

src/sound/gs.v

@@ -5,12 +5,13 @@
   -----------------------------------------------------------------------------
    18.08.2018	Reworked first verilog version
    19.08.2018	Produce proper signed output
-  
+   20.08.2018	Use external SDR/DDR RAM for page 2 and up
+
    CPU: Z80 @ 28MHz
    ROM: 32K
-   RAM: 128KB+
+   RAM: up to 4096KB
    INT: 37.5KHz
-  
+
    #xxBB Command register - регистр команд, доступный для записи
    #xxBB Status register - регистр состояния, доступный для чтения
   		bit 7 флаг данных
@@ -65,7 +66,7 @@
 
 */
 
-module gs #(parameter PAGES=4, ROMFILE="gs105b.mif")
+module gs #(parameter ROMFILE="gs105b.mif")
 (
    input         RESET,
    input         CLK,
@@ -222,7 +223,7 @@ assign MEM_WR   = mem_wr && |page_addr[6:1];
 assign MEM_DI   = cpu_do_bus;
 
 wire [7:0] mem_do;
-dpram #(.ADDRWIDTH(16), .NUMWORDS(2*32768), .MEM_INIT_FILE(ROMFILE)) mem
+dpram #(.ADDRWIDTH(16), .MEM_INIT_FILE(ROMFILE)) mem
 (
 	.clock(CLK),
 	.address_a(MEM_ADDR[15:0]),

src/tsconf.v

@@ -778,13 +778,12 @@ zint TS13
 );
    
 // ROM
-gen_rom #(.init_file("src/loader_fat32/loader.mif"), .addr_width(13)) SE1
+dpram #(.ADDRWIDTH(13), .MEM_INIT_FILE("src/loader_fat32/loader.mif")) SE1
-(
+(
-	.wrclock(clk_28mhz),
+	.clock(clk_28mhz),
-	.rdclock(clk_28mhz),
+	.address_a(cpu_a_bus[12:0]),
-	.rdaddress(cpu_a_bus[12:0]),
+	.q_a(rom_do_bus)
-	.q(rom_do_bus)
+);
-);
    
 // SDRAM Controller
 sdram SE4
@@ -893,7 +892,7 @@ always @(posedge clk_84mhz) begin
 	if(ce_gs) ce_gs <= 0;
 end
 
-gs #(.PAGES(4), .ROMFILE("src/sound/gs105b.mif")) U15
+gs #("src/sound/gs105b.mif") U15
 (
 	.RESET(reset),
 	.CLK(clk_84mhz),