diff --git a/TSConf-lite.srf b/TSConf-lite.srf index 7e6f24f..8f27398 100644 --- a/TSConf-lite.srf +++ b/TSConf-lite.srf @@ -18,6 +18,8 @@ { "" "" "" "Inferred RAM node \"emu:emu\|tsconf:tsconf\|T80s:z80_unit\|T80:u0\|T80_Reg:Regs\|RegsH_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "Inferred RAM node \"emu:emu\|tsconf:tsconf\|T80s:z80_unit\|T80:u0\|T80_Reg:Regs\|RegsL_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|tsconf:tsconf\|gs:U15\|T80s:z80_unit\|T80:u0\|T80_Reg:Regs\|RegsH_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|tsconf:tsconf\|gs:U15\|T80s:z80_unit\|T80:u0\|T80_Reg:Regs\|RegsL_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "*" { } { } 0 21074 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} { "" "" "" "sysmem_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/TSConf.sv b/TSConf.sv index 45879ab..1bf8ae4 100644 --- a/TSConf.sv +++ b/TSConf.sv @@ -152,7 +152,6 @@ wire locked; wire clk_mem; wire clk_sys; wire clk_28m; -wire clk_21m; pll pll ( @@ -162,7 +161,6 @@ pll pll .outclk_1(SDRAM_CLK), .outclk_2(clk_sys), .outclk_3(clk_28m), - .outclk_4(clk_21m), .locked(locked) ); @@ -240,7 +238,6 @@ tsconf tsconf ( .clk_84mhz(clk_mem), .clk_28mhz(clk_28m), - .clk_21mhz(clk_21m), .SDRAM_DQ(SDRAM_DQ), .SDRAM_A(SDRAM_A), diff --git a/src/sound/gs.vhd b/src/sound/gs.vhd index 1e2f218..22d1cc1 100644 --- a/src/sound/gs.vhd +++ b/src/sound/gs.vhd @@ -74,7 +74,7 @@ entity gs is Port ( RESET : in std_logic; CLK : in std_logic; - CLKGS : in std_logic; + CE : in std_logic; A : in std_logic_vector(15 downto 0); DI : in std_logic_vector(7 downto 0); DO : out std_logic_vector(7 downto 0); @@ -135,7 +135,8 @@ generic map ( IOWait => 1) -- 0 => Single cycle I/O, 1 => Std I/O cycle port map ( RESET_n => not RESET, - CLK_n => not CLKGS, + CLK_n => CLK, + CEN => CE, WAIT_n => '1', INT_n => int_n, NMI_n => '1', @@ -145,37 +146,31 @@ port map ( IORQ_n => cpu_iorq_n, RD_n => cpu_rd_n, WR_n => cpu_wr_n, - RFSH_n => open, - HALT_n => open, - BUSAK_n => open, A => cpu_a_bus, DI => cpu_di_bus, - DO => cpu_do_bus, - SavePC => open, - SaveINT => open, - RestorePC => (others => '1'), - RestoreINT => (others => '1'), - RestorePC_n => '1'); + DO => cpu_do_bus); -- INT# -process (CLKGS) +process (CLK) begin - if rising_edge(CLKGS) then - cnt <= cnt + 1; - if cnt = "1000110000" then -- 21MHz / 560 = 0.0375MHz = 37.5kHz - cnt <= (others => '0'); - int_n <= '0'; - end if; - if cpu_iorq_n = '0' and cpu_m1_n = '0' then - int_n <= '1'; + if rising_edge(CLK) then + if CE = '1' then + cnt <= cnt + 1; + if cnt = "1011101010" then -- 28MHz / 747 = 0.03748MHz = 37.48kHz + cnt <= (others => '0'); + int_n <= '0'; + end if; + if cpu_iorq_n = '0' and cpu_m1_n = '0' then + int_n <= '1'; + end if; end if; end if; end process; -process (CLKGS) +process (CLK) begin - if rising_edge(CLKGS) then + if rising_edge(CLK) then if (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"2") or (IORQ_n = '0' and RD_n = '0' and A(7 downto 0) = X"B3") then bit7_flag <= '0'; elsif (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"3") or (IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"B3") then @@ -186,9 +181,9 @@ begin end if; end process; -process (CLKGS) +process (CLK) begin - if rising_edge(CLKGS) then + if rising_edge(CLK) then if cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"5" then bit0_flag <= '0'; elsif IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"BB" then @@ -216,9 +211,9 @@ end process; -- port #xxBB / #xxB3 DO <= bit7_flag & "111111" & bit0_flag when A(3) = '1' else port_xx03_reg; -process (CLKGS) +process (CLK) begin - if rising_edge(CLKGS) then + if rising_edge(CLK) then if RESET = '1' then port_xx00_reg <= (others => '0'); port_xx03_reg <= (others => '0'); @@ -230,7 +225,7 @@ begin ch_b_reg <= (others => '0'); ch_c_reg <= (others => '0'); ch_d_reg <= (others => '0'); - else + elsif CE = '1' then if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"0" then port_xx00_reg <= cpu_do_bus; end if; if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"3" then port_xx03_reg <= cpu_do_bus; end if; if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"6" then port_xx06_reg <= cpu_do_bus(5 downto 0); end if; @@ -275,8 +270,8 @@ generic map ) port map ( - wrclock => CLKGS, - rdclock => CLKGS, + wrclock => CLK, + rdclock => CLK, rdaddress => cpu_a_bus(14 downto 0), q => rom_do ); @@ -288,7 +283,7 @@ generic map ( ) port map ( - clk => CLKGS, + clk => CLK, we => ram_we and not ram_addr(18), addr => ram_addr(17 downto 0), d => cpu_do_bus, @@ -302,28 +297,32 @@ generic map ( ) port map ( - clk => CLKGS, + clk => CLK, we => ram_we and ram_addr(18) and not ram_addr(17), addr => ram_addr(16 downto 0), d => cpu_do_bus, q => ram2_do ); -process (CLKGS) +process (CLK) begin - if rising_edge(CLKGS) then - out_a <= ch_a_reg * port_xx06_reg; - out_b <= ch_b_reg * port_xx07_reg; - out_c <= ch_c_reg * port_xx08_reg; - out_d <= ch_d_reg * port_xx09_reg; + if rising_edge(CLK) then + if CE = '1' then + out_a <= ch_a_reg * port_xx06_reg; + out_b <= ch_b_reg * port_xx07_reg; + out_c <= ch_c_reg * port_xx08_reg; + out_d <= ch_d_reg * port_xx09_reg; + end if; end if; end process; -process (CLKGS) +process (CLK) begin - if rising_edge(CLKGS) then - OUTL <= ('0'&out_a) + ('0'&out_b); - OUTR <= ('0'&out_c) + ('0'&out_d); + if rising_edge(CLK) then + if CE = '1' then + OUTL <= ('0'&out_a) + ('0'&out_b); + OUTR <= ('0'&out_c) + ('0'&out_d); + end if; end if; end process; diff --git a/src/t80/T80s.vhd b/src/t80/T80s.vhd index df6bd14..d68b64d 100644 --- a/src/t80/T80s.vhd +++ b/src/t80/T80s.vhd @@ -78,35 +78,34 @@ entity T80s is ); port( RESET_n : in std_logic; - CLK_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; BUSRQ_n : in std_logic; - M1_n : out std_logic; + M1_n : out std_logic; MREQ_n : out std_logic; IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; RFSH_n : out std_logic; HALT_n : out std_logic; BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); SavePC : out std_logic_vector(15 downto 0); SaveINT : out std_logic_vector(7 downto 0); - RestorePC : in std_logic_vector(15 downto 0); - RestoreINT : in std_logic_vector(7 downto 0); - - RestorePC_n : in std_logic + RestorePC : in std_logic_vector(15 downto 0) := (others => '1'); + RestoreINT : in std_logic_vector(7 downto 0) := (others => '1'); + RestorePC_n : in std_logic := '1' ); end T80s; architecture rtl of T80s is - signal CEN : std_logic; signal IntCycle_n : std_logic; signal NoRead : std_logic; signal Write : std_logic; @@ -117,8 +116,6 @@ architecture rtl of T80s is begin - CEN <= '1'; - u0 : T80 generic map( Mode => Mode, @@ -161,43 +158,45 @@ begin IORQ_n <= '1'; MREQ_n <= '1'; DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; end if; else - if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then - WR_n <= '0'; + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; IORQ_n <= not IORQ; MREQ_n <= IORQ; end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; end if; end process; diff --git a/src/tsconf.vhd b/src/tsconf.vhd index 9ee6690..48cd85d 100644 --- a/src/tsconf.vhd +++ b/src/tsconf.vhd @@ -63,7 +63,6 @@ port -- Clocks clk_84mhz : in std_logic; clk_28mhz : in std_logic; - clk_21mhz : in std_logic; -- SDRAM (32MB 16x16bit) SDRAM_DQ : inout std_logic_vector(15 downto 0); @@ -863,6 +862,7 @@ generic map ( port map ( RESET_n => not reset, CLK_n => zclk, + CEN => '1', WAIT_n => '1', INT_n => cpu_int_n_TS, NMI_n => '1', @@ -873,16 +873,9 @@ port map ( RD_n => cpu_rd_n, WR_n => cpu_wr_n, RFSH_n => cpu_rfsh_n, - HALT_n => open, - BUSAK_n => open, A => cpu_a_bus, DI => cpu_di_bus, - DO => cpu_do_bus, - SavePC => open, - SaveINT => open, - RestorePC => (others => '1'), - RestoreINT => (others => '1'), - RestorePC_n => '1'); + DO => cpu_do_bus); TS04: zsignals port map ( @@ -1393,7 +1386,7 @@ U15: entity work.gs port map ( RESET => reset or not GS_ENA, CLK => clk_28mhz, - CLKGS => clk_21mhz, + CE => '1', A => cpu_a_bus, DI => cpu_do_bus, DO => gs_do_bus, diff --git a/sys/pll.qip b/sys/pll.qip index c09cfc0..4f330f6 100644 --- a/sys/pll.qip +++ b/sys/pll.qip @@ -35,8 +35,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NQ==::TnVtYmVyIE9mIENsb2Nrcw==" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NQ==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NA==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NA==::bnVtYmVyX29mX2Nsb2Nrcw==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" @@ -268,7 +268,7 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MjguMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MjEuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" @@ -317,8 +317,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" -set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTIsMTEsMjU2LDI1NixmYWxzZSx0cnVlLHRydWUsZmFsc2UsNyw3LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDcsNyw5LDcscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxMSwxMCwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDIxLDIxLDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDI4LDI4LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMjAsNDAwMCwxMTc2LjAgTUh6LDIyMzMzODI5OTQsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTIsMTEsMjU2LDI1NixmYWxzZSx0cnVlLHRydWUsZmFsc2UsNyw3LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDcsNyw5LDcscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxMSwxMCwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDIxLDIxLDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMjAsNDAwMCwxMTc2LjAgTUh6LDIyMzMzODI5OTQsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw==" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" diff --git a/sys/pll.v b/sys/pll.v index 7bd6c76..bc7a7b9 100644 --- a/sys/pll.v +++ b/sys/pll.v @@ -12,7 +12,6 @@ module pll ( output wire outclk_1, // outclk1.clk output wire outclk_2, // outclk2.clk output wire outclk_3, // outclk3.clk - output wire outclk_4, // outclk4.clk output wire locked // locked.export ); @@ -23,7 +22,6 @@ module pll ( .outclk_1 (outclk_1), // outclk1.clk .outclk_2 (outclk_2), // outclk2.clk .outclk_3 (outclk_3), // outclk3.clk - .outclk_4 (outclk_4), // outclk4.clk .locked (locked) // locked.export ); @@ -69,7 +67,7 @@ endmodule // Retrieval info: // Retrieval info: // Retrieval info: -// Retrieval info: +// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: diff --git a/sys/pll/pll_0002.v b/sys/pll/pll_0002.v index 2e44880..0063726 100644 --- a/sys/pll/pll_0002.v +++ b/sys/pll/pll_0002.v @@ -19,9 +19,6 @@ module pll_0002( // interface 'outclk3' output wire outclk_3, - // interface 'outclk4' - output wire outclk_4, - // interface 'locked' output wire locked ); @@ -30,7 +27,7 @@ module pll_0002( .fractional_vco_multiplier("true"), .reference_clock_frequency("50.0 MHz"), .operation_mode("direct"), - .number_of_clocks(5), + .number_of_clocks(4), .output_clock_frequency0("84.000000 MHz"), .phase_shift0("0 ps"), .duty_cycle0(50), @@ -43,7 +40,7 @@ module pll_0002( .output_clock_frequency3("28.000000 MHz"), .phase_shift3("0 ps"), .duty_cycle3(50), - .output_clock_frequency4("21.000000 MHz"), + .output_clock_frequency4("0 MHz"), .phase_shift4("0 ps"), .duty_cycle4(50), .output_clock_frequency5("0 MHz"), @@ -89,7 +86,7 @@ module pll_0002( .pll_subtype("General") ) altera_pll_i ( .rst (rst), - .outclk ({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}), + .outclk ({outclk_3, outclk_2, outclk_1, outclk_0}), .locked (locked), .fboutclk ( ), .fbclk (1'b0),