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https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 14:51:25 +03:00
Remove redundant CPU signals.
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@ -73,7 +73,7 @@ use work.T80_Pack.all;
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entity T80s is
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generic(
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Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
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T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
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IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
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);
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port(
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@ -94,13 +94,7 @@ entity T80s is
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BUSAK_n : out std_logic;
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A : out std_logic_vector(15 downto 0);
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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SavePC : out std_logic_vector(15 downto 0);
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SaveINT : out std_logic_vector(7 downto 0);
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RestorePC : in std_logic_vector(15 downto 0) := (others => '1');
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RestoreINT : in std_logic_vector(7 downto 0) := (others => '1');
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RestorePC_n : in std_logic := '1'
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DO : out std_logic_vector(7 downto 0)
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);
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end T80s;
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@ -143,12 +137,12 @@ begin
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TS => TState,
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IntCycle_n => IntCycle_n,
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SavePC => SavePC,
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SaveINT => SaveINT,
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RestorePC => RestorePC,
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RestoreINT => RestoreINT,
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SavePC => open,
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SaveINT => open,
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RestorePC => (others => '1'),
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RestoreINT => (others => '1'),
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RestorePC_n => RestorePC_n );
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RestorePC_n => '1' );
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process (RESET_n, CLK_n)
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begin
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