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Remove redundant CPU signals.

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This commit is contained in:
sorgelig
2018-08-19 23:29:23 +08:00
parent 44f8d8176e
commit 412901568b
1 changed files with 9 additions and 15 deletions
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24
src/t80/T80s.vhd
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@ -72,9 +72,9 @@ use work.T80_Pack.all;
entity T80s is entity T80s is
generic( generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
); );
port( port(
RESET_n : in std_logic; RESET_n : in std_logic;
@ -94,13 +94,7 @@ entity T80s is
BUSAK_n : out std_logic; BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0); A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0); DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0); DO : out std_logic_vector(7 downto 0)
SavePC : out std_logic_vector(15 downto 0);
SaveINT : out std_logic_vector(7 downto 0);
RestorePC : in std_logic_vector(15 downto 0) := (others => '1');
RestoreINT : in std_logic_vector(7 downto 0) := (others => '1');
RestorePC_n : in std_logic := '1'
); );
end T80s; end T80s;
@ -143,12 +137,12 @@ begin
TS => TState, TS => TState,
IntCycle_n => IntCycle_n, IntCycle_n => IntCycle_n,
SavePC => SavePC, SavePC => open,
SaveINT => SaveINT, SaveINT => open,
RestorePC => RestorePC, RestorePC => (others => '1'),
RestoreINT => RestoreINT, RestoreINT => (others => '1'),
RestorePC_n => RestorePC_n ); RestorePC_n => '1' );
process (RESET_n, CLK_n) process (RESET_n, CLK_n)
begin begin