mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 23:01:37 +03:00
add zifi
This commit is contained in:
Eugene Lozovoy
149
rtl/periph/uart_rx.v
Normal file
149
rtl/periph/uart_rx.v
Normal file
@ -0,0 +1,149 @@
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//////////////////////////////////////////////////////////////////////
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// File Downloaded from http://www.nandland.com
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//////////////////////////////////////////////////////////////////////
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// This file contains the UART Receiver. This receiver is able to
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// receive 8 bits of serial data, one start bit, one stop bit,
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// and no parity bit. When receive is complete o_rx_dv will be
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// driven high for one clock cycle.
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//
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// Set Parameter CLKS_PER_BIT as follows:
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// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
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// Example: 10 MHz Clock, 115200 baud UART
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// (10000000)/(115200) = 87
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module uart_rx
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#(parameter CLKS_PER_BIT)
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(
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input i_Clock,
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input i_Rx_Serial,
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output o_Rx_DV,
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output [7:0] o_Rx_Byte
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);
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localparam s_IDLE = 3'b000;
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localparam s_RX_START_BIT = 3'b001;
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localparam s_RX_DATA_BITS = 3'b010;
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localparam s_RX_STOP_BIT = 3'b011;
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localparam s_CLEANUP = 3'b100;
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reg r_Rx_Data_R = 1'b1;
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reg r_Rx_Data = 1'b1;
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reg [7:0] r_Clock_Count = 0;
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reg [2:0] r_Bit_Index = 0; //8 bits total
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reg [7:0] r_Rx_Byte = 0;
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reg r_Rx_DV = 0;
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reg [2:0] r_SM_Main = 0;
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// Purpose: Double-register the incoming data.
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// This allows it to be used in the UART RX Clock Domain.
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// (It removes problems caused by metastability)
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always @(posedge i_Clock)
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begin
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r_Rx_Data_R <= i_Rx_Serial;
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r_Rx_Data <= r_Rx_Data_R;
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end
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// Purpose: Control RX state machine
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always @(posedge i_Clock)
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begin
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case (r_SM_Main)
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s_IDLE :
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begin
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r_Rx_DV <= 1'b0;
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r_Clock_Count <= 0;
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r_Bit_Index <= 0;
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if (r_Rx_Data == 1'b0) // Start bit detected
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r_SM_Main <= s_RX_START_BIT;
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else
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r_SM_Main <= s_IDLE;
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end
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// Check middle of start bit to make sure it's still low
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s_RX_START_BIT :
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begin
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if (r_Clock_Count == (CLKS_PER_BIT-1)/2)
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begin
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if (r_Rx_Data == 1'b0)
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begin
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r_Clock_Count <= 0; // reset counter, found the middle
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r_SM_Main <= s_RX_DATA_BITS;
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end
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else
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r_SM_Main <= s_IDLE;
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end
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else
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begin
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r_Clock_Count <= r_Clock_Count + 1'd1;
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r_SM_Main <= s_RX_START_BIT;
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end
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end // case: s_RX_START_BIT
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// Wait CLKS_PER_BIT-1 clock cycles to sample serial data
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s_RX_DATA_BITS :
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begin
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if (r_Clock_Count < CLKS_PER_BIT-1)
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begin
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r_Clock_Count <= r_Clock_Count + 1'd1;
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r_SM_Main <= s_RX_DATA_BITS;
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end
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else
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begin
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r_Clock_Count <= 0;
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r_Rx_Byte[r_Bit_Index] <= r_Rx_Data;
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// Check if we have received all bits
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if (r_Bit_Index < 7)
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begin
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r_Bit_Index <= r_Bit_Index + 1'd1;
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r_SM_Main <= s_RX_DATA_BITS;
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end
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else
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begin
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r_Bit_Index <= 0;
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r_SM_Main <= s_RX_STOP_BIT;
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end
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end
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end // case: s_RX_DATA_BITS
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// Receive Stop bit. Stop bit = 1
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s_RX_STOP_BIT :
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begin
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// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
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if (r_Clock_Count < CLKS_PER_BIT-1)
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begin
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r_Clock_Count <= r_Clock_Count + 1'd1;
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r_SM_Main <= s_RX_STOP_BIT;
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end
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else
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begin
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r_Rx_DV <= 1'b1;
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r_Clock_Count <= 0;
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r_SM_Main <= s_CLEANUP;
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end
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end // case: s_RX_STOP_BIT
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// Stay here 1 clock
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s_CLEANUP :
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begin
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r_SM_Main <= s_IDLE;
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r_Rx_DV <= 1'b0;
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end
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default :
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r_SM_Main <= s_IDLE;
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endcase
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end
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assign o_Rx_DV = r_Rx_DV;
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assign o_Rx_Byte = r_Rx_Byte;
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endmodule // uart_rx
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146
rtl/periph/uart_tx.v
Normal file
146
rtl/periph/uart_tx.v
Normal file
@ -0,0 +1,146 @@
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//////////////////////////////////////////////////////////////////////
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// File Downloaded from http://www.nandland.com
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//////////////////////////////////////////////////////////////////////
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// This file contains the UART Transmitter. This transmitter is able
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// to transmit 8 bits of serial data, one start bit, one stop bit,
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// and no parity bit. When transmit is complete o_Tx_done will be
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// driven high for one clock cycle.
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//
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// Set Parameter CLKS_PER_BIT as follows:
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// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
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// Example: 10 MHz Clock, 115200 baud UART
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// (10000000)/(115200) = 87
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module uart_tx
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#(parameter CLKS_PER_BIT)
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(
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input i_Clock,
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input i_Tx_DV,
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input [7:0] i_Tx_Byte,
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output o_Tx_Active,
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output reg o_Tx_Serial,
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output o_Tx_Done
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);
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localparam s_IDLE = 3'b000;
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localparam s_TX_START_BIT = 3'b001;
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localparam s_TX_DATA_BITS = 3'b010;
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localparam s_TX_STOP_BIT = 3'b011;
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localparam s_CLEANUP = 3'b100;
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reg [2:0] r_SM_Main = 0;
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reg [7:0] r_Clock_Count = 0;
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reg [2:0] r_Bit_Index = 0;
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reg [7:0] r_Tx_Data = 0;
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reg r_Tx_Done = 0;
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reg r_Tx_Active = 0;
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always @(posedge i_Clock)
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begin
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case (r_SM_Main)
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s_IDLE :
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begin
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o_Tx_Serial <= 1'b1; // Drive Line High for Idle
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r_Tx_Done <= 1'b0;
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r_Clock_Count <= 0;
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r_Bit_Index <= 0;
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if (i_Tx_DV == 1'b1)
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begin
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r_Tx_Active <= 1'b1;
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r_Tx_Data <= i_Tx_Byte;
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r_SM_Main <= s_TX_START_BIT;
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end
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else
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r_SM_Main <= s_IDLE;
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end // case: s_IDLE
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// Send out Start Bit. Start bit = 0
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s_TX_START_BIT :
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begin
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o_Tx_Serial <= 1'b0;
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// Wait CLKS_PER_BIT-1 clock cycles for start bit to finish
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if (r_Clock_Count < CLKS_PER_BIT-1)
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begin
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r_Clock_Count <= r_Clock_Count + 1'd1;
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r_SM_Main <= s_TX_START_BIT;
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end
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else
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begin
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r_Clock_Count <= 0;
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r_SM_Main <= s_TX_DATA_BITS;
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end
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end // case: s_TX_START_BIT
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// Wait CLKS_PER_BIT-1 clock cycles for data bits to finish
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s_TX_DATA_BITS :
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begin
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o_Tx_Serial <= r_Tx_Data[r_Bit_Index];
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if (r_Clock_Count < CLKS_PER_BIT-1)
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begin
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r_Clock_Count <= r_Clock_Count + 1'd1;
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r_SM_Main <= s_TX_DATA_BITS;
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end
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else
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begin
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r_Clock_Count <= 0;
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// Check if we have sent out all bits
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if (r_Bit_Index < 7)
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begin
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r_Bit_Index <= r_Bit_Index + 1'd1;
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r_SM_Main <= s_TX_DATA_BITS;
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end
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else
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begin
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r_Bit_Index <= 0;
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r_SM_Main <= s_TX_STOP_BIT;
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end
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end
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end // case: s_TX_DATA_BITS
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// Send out Stop bit. Stop bit = 1
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s_TX_STOP_BIT :
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begin
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o_Tx_Serial <= 1'b1;
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// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
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if (r_Clock_Count < CLKS_PER_BIT-1)
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begin
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r_Clock_Count <= r_Clock_Count + 1'd1;
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r_SM_Main <= s_TX_STOP_BIT;
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end
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else
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begin
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r_Tx_Done <= 1'b1;
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r_Clock_Count <= 0;
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r_SM_Main <= s_CLEANUP;
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r_Tx_Active <= 1'b0;
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end
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end // case: s_Tx_STOP_BIT
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// Stay here 1 clock
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s_CLEANUP :
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begin
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r_Tx_Done <= 1'b1;
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r_SM_Main <= s_IDLE;
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end
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default :
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r_SM_Main <= s_IDLE;
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endcase
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end
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assign o_Tx_Active = r_Tx_Active;
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assign o_Tx_Done = r_Tx_Done;
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endmodule
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252
rtl/periph/zifi.v
Normal file
252
rtl/periph/zifi.v
Normal file
@ -0,0 +1,252 @@
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module zifi
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(
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input clk,
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input rst,
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input wire [ 7:0] din,
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output reg [ 7:0] dout,
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output reg dataout = 0,
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input wire [15:0] a,
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input iord,
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input iord_s,
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input iowr_s,
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input rx,
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output tx
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);
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/*--------------------------------------------------------------------------------
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https://github.com/HackerVBI/ZiFi/blob/master/_esp/upd1/README!!__eRS232.txt
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Address Mode Name Description
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0x00EF..0xBFEF R DR Data register (ZIFI or RS232).
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Get byte from input FIFO.
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Input FIFO must not be empty (xx_IFR > 0).
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0x00EF..0xBFEF W DR Data register (ZIFI or RS232).
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Put byte into output FIFO.
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Output FIFO must not be full (xx_OFR > 0).
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Address Mode Name Description
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0xC0EF R ZF_IFR ZIFI Input FIFO Used Register. Switch DR to ZIFI FIFO.
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0 - input FIFO is empty, 191 - input FIFO contain 191 or more bytes.
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0xC1EF R ZF_OFR ZIFI Output FIFO Free Register. Switch DR to ZIFI FIFO.
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0 - output FIFO is full, 191 - output FIFO free 191 or more bytes.
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0xC2EF R RS_IFR RS232 Input FIFO Used Register. Switch DR to RS232 FIFO.
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0 - input FIFO is empty, 191 - input FIFO contain 191 or more bytes.
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0xC3EF R RS_OFR RS232 Output FIFO Free Register. Switch DR to RS232 FIFO.
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0 - output FIFO is full, 191 - output FIFO free 191 or more bytes.
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Address Mode Name Description
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0xC7EF W CR Command register. Command set depends on API mode selected.
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All mode commands:
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Code Command Description
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000000oi Clear ZIFI FIFOs
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i: 1 - clear input ZIFI FIFO,
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o: 1 - clear output ZIFI FIFO.
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000001oi Clear RS232 FIFOs
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i: 1 - clear input RS232 FIFO,
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o: 1 - clear output RS232 FIFO.
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11110mmm Set API mode or disable API:
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0 API disabled.
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1 transparent: all data is sent/received to/from external UART directly.
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2..7 reserved.
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11111111 Get Version Returns highest supported API version. ER=0xFF - no API available.
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Address Mode Name Description
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0xC7EF R ER Error register - command execution result code. Depends on command issued.
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All mode responses:
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Code Description
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0x00 OK - no error.
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0xFF REJ - command rejected.
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--------------------------------------------------------------------------------*/
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localparam DR = 16'h??EF;
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localparam ZF_IFR = 16'hC0EF;
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localparam ZF_OFR = 16'hC1EF;
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localparam RS_IFR = 16'hC2EF;
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localparam RS_OFR = 16'hC3EF;
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localparam CR = 16'hC7EF;
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localparam ER = 16'hC7EF;
|
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reg [7:0] er;
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reg zifi_en;
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always @(posedge clk) begin
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dataout <= dataout & iord;
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fifo_rx_rdreq <= 1'b0;
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fifo_tx_wrreq <= 1'b0;
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fifo_rx_sclr <= 1'b0;
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fifo_tx_sclr <= 1'b0;
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||||
|
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if (iord_s) begin
|
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casez (a)
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ZF_IFR: begin
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||||
dataout <= 1'b1;
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dout <= rx_busy? 8'd0 : ((fifo_rx_usedw < 191)? fifo_rx_usedw[7:0] : 8'd191);
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zifi_en <= 1'b1;
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||||
end
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ZF_OFR: begin
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dataout <= 1'b1;
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||||
dout <= (fifo_tx_freew < 191)? fifo_tx_freew[7:0] : 8'd191;
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zifi_en <= 1'b1;
|
||||
end
|
||||
RS_IFR: begin
|
||||
dataout <= 1'b1;
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||||
dout <= 8'd0;
|
||||
zifi_en <= 1'b0;
|
||||
end
|
||||
RS_OFR: begin
|
||||
dataout <= 1'b1;
|
||||
dout <= 8'd191;
|
||||
zifi_en <= 1'b0;
|
||||
end
|
||||
ER: begin
|
||||
dataout <= 1'b1;
|
||||
dout <= er;
|
||||
end
|
||||
DR: begin
|
||||
dataout <= 1'b1;
|
||||
dout <= fifo_rx_q;
|
||||
fifo_rx_rdreq <= zifi_en;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
if (iowr_s) begin
|
||||
casez (a)
|
||||
CR: begin
|
||||
casez (din)
|
||||
8'b000000??: begin
|
||||
fifo_rx_sclr <= din[0];
|
||||
fifo_tx_sclr <= din[1];
|
||||
er <= 8'h00;
|
||||
end
|
||||
8'b000001??: begin
|
||||
er <= 8'h00;
|
||||
end
|
||||
8'b11110???: begin
|
||||
er <= 8'h00;
|
||||
end
|
||||
8'b11111111: begin
|
||||
er <= 8'h01;
|
||||
end
|
||||
default: begin
|
||||
er <= 8'hFF;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
DR: begin
|
||||
fifo_tx_data <= din;
|
||||
fifo_tx_wrreq <= zifi_en;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
// workarround to fix random hang of zifi.spg (a2cfe54), which is always doing 191-bytes-inir (see fifo_inir function)
|
||||
reg [19:0] rx_busy_cnt = 0;
|
||||
reg rx_busy = 0;
|
||||
always @(posedge clk) begin
|
||||
if (fifo_rx_wrreq)
|
||||
rx_busy_cnt <= 1'd1;
|
||||
else if (rx_busy_cnt)
|
||||
rx_busy_cnt <= rx_busy_cnt + 1'd1;
|
||||
rx_busy <= (fifo_rx_wrreq || rx_busy_cnt) && fifo_rx_usedw < 191;
|
||||
end
|
||||
|
||||
|
||||
wire [7:0] fifo_rx_data;
|
||||
wire fifo_rx_wrreq;
|
||||
reg fifo_rx_rdreq;
|
||||
reg fifo_rx_sclr;
|
||||
wire [7:0] fifo_rx_q;
|
||||
wire [12:0] fifo_rx_usedw;
|
||||
scfifo
|
||||
#(
|
||||
.lpm_width(8),
|
||||
.lpm_widthu(13),
|
||||
.lpm_numwords(8192),
|
||||
.lpm_showahead("ON"),
|
||||
.overflow_checking("ON"),
|
||||
.underflow_checking("ON"),
|
||||
.add_ram_output_register("OFF")
|
||||
)
|
||||
fifo_rx
|
||||
(
|
||||
.clock(clk),
|
||||
.data(fifo_rx_data),
|
||||
.wrreq(fifo_rx_wrreq),
|
||||
.rdreq(fifo_rx_rdreq),
|
||||
.sclr(rst | fifo_rx_sclr),
|
||||
.q(fifo_rx_q),
|
||||
.usedw(fifo_rx_usedw)
|
||||
);
|
||||
|
||||
|
||||
reg [7:0] fifo_tx_data;
|
||||
reg fifo_tx_wrreq;
|
||||
wire fifo_tx_rdreq;
|
||||
reg fifo_tx_sclr;
|
||||
wire [7:0] fifo_tx_q;
|
||||
wire [7:0] fifo_tx_usedw;
|
||||
wire [7:0] fifo_tx_freew = 8'h255 - fifo_tx_usedw;
|
||||
wire fifo_tx_empty;
|
||||
reg fifo_tx_empty_r;
|
||||
always @(posedge clk)
|
||||
fifo_tx_empty_r <= fifo_tx_empty;
|
||||
scfifo
|
||||
#(
|
||||
.lpm_width(8),
|
||||
.lpm_widthu(8),
|
||||
.lpm_numwords(256),
|
||||
.lpm_showahead("ON"),
|
||||
.overflow_checking("ON"),
|
||||
.underflow_checking("ON"),
|
||||
.add_ram_output_register("OFF")
|
||||
)
|
||||
fifo_tx
|
||||
(
|
||||
.clock(clk),
|
||||
.data(fifo_tx_data),
|
||||
.wrreq(fifo_tx_wrreq),
|
||||
.rdreq(fifo_tx_rdreq),
|
||||
.sclr(rst | fifo_tx_sclr),
|
||||
.q(fifo_tx_q),
|
||||
.usedw(fifo_tx_usedw),
|
||||
.empty(fifo_tx_empty)
|
||||
);
|
||||
|
||||
|
||||
uart_rx #(.CLKS_PER_BIT(28_000_000/115200)) uart_rx
|
||||
(
|
||||
.i_Clock(clk),
|
||||
.i_Rx_Serial(rx),
|
||||
.o_Rx_DV(fifo_rx_wrreq),
|
||||
.o_Rx_Byte(fifo_rx_data)
|
||||
);
|
||||
|
||||
|
||||
wire tx_busy;
|
||||
reg tx_busy_r;
|
||||
always @(posedge clk)
|
||||
tx_busy_r <= tx_busy;
|
||||
assign fifo_tx_rdreq = tx_busy && !tx_busy_r;
|
||||
uart_tx #(.CLKS_PER_BIT(28_000_000/115200)) uart_tx
|
||||
(
|
||||
.i_Clock(clk),
|
||||
.i_Tx_DV(!fifo_tx_empty_r),
|
||||
.i_Tx_Byte(fifo_tx_q),
|
||||
.o_Tx_Active(tx_busy),
|
||||
.o_Tx_Serial(tx),
|
||||
.o_Tx_Done()
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
23
rtl/tsconf.v
23
rtl/tsconf.v
@ -47,6 +47,8 @@ module tsconf
|
||||
input TAPE_IN,
|
||||
output TAPE_OUT,
|
||||
output MIDI_OUT,
|
||||
input UART_RX,
|
||||
output UART_TX,
|
||||
|
||||
// Configuration bits
|
||||
input CFG_OUT0,
|
||||
@ -979,6 +981,26 @@ module tsconf
|
||||
);
|
||||
|
||||
|
||||
// ZiFi
|
||||
wire [7:0] zifi_do;
|
||||
wire zifi_dataout;
|
||||
|
||||
zifi zifi
|
||||
(
|
||||
.clk(fclk),
|
||||
.rst(rst),
|
||||
.din(d),
|
||||
.dout(zifi_do),
|
||||
.dataout(zifi_dataout),
|
||||
.a(a),
|
||||
.iord(iord),
|
||||
.iord_s(iord_s),
|
||||
.iowr_s(iowr_s),
|
||||
.rx(UART_RX),
|
||||
.tx(UART_TX)
|
||||
);
|
||||
|
||||
|
||||
// Soundrive
|
||||
wire [7:0] covox_a;
|
||||
wire [7:0] covox_b;
|
||||
@ -1126,6 +1148,7 @@ module tsconf
|
||||
(~mreq_n && ~rd_n) ? dout_ram : // SDRAM
|
||||
(gs_sel && ~rd_n) ? gs_do_bus : // General Sound
|
||||
(ts_enable && ~rd_n) ? ts_do : // TurboSound
|
||||
(zifi_dataout && ~rd_n) ? zifi_do : // ZiFi
|
||||
(ena_ports) ? dout_ports :
|
||||
(intack) ? im2vect :
|
||||
8'b11111111;
|
||||
|
||||
Reference in New Issue
Block a user