uzix/TSConf_MiST
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Convert tsconf.vhd to verilog for easier maintanance.

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sorgelig
2018-08-20 00:47:23 +08:00
parent 550ee59c7e
commit 398cb1e4d1
4 changed files with 1005 additions and 1556 deletions
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2
TSConf-lite.qsf
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@ -399,7 +399,7 @@ set_global_assignment -name VERILOG_FILE src/kempston_mouse.v
set_global_assignment -name VERILOG_FILE src/spi.v set_global_assignment -name VERILOG_FILE src/spi.v
set_global_assignment -name VHDL_FILE src/sdram.vhd set_global_assignment -name VHDL_FILE src/sdram.vhd
set_global_assignment -name VERILOG_FILE src/clock.v set_global_assignment -name VERILOG_FILE src/clock.v
set_global_assignment -name VHDL_FILE src/tsconf.vhd set_global_assignment -name VERILOG_FILE src/tsconf.v
set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv
set_global_assignment -name VERILOG_FILE dpram.v set_global_assignment -name VERILOG_FILE dpram.v
set_global_assignment -name SYSTEMVERILOG_FILE TSConf.sv set_global_assignment -name SYSTEMVERILOG_FILE TSConf.sv

6
TSConf.qsf
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@ -357,6 +357,7 @@ set_location_assignment PIN_W21 -to SW[2]
set_location_assignment PIN_W20 -to SW[3] set_location_assignment PIN_W20 -to SW[3]
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name QSYS_FILE sys/vip.qsys set_global_assignment -name QSYS_FILE sys/vip.qsys
@ -404,7 +405,8 @@ set_global_assignment -name VERILOG_FILE src/kempston_mouse.v
set_global_assignment -name VERILOG_FILE src/spi.v set_global_assignment -name VERILOG_FILE src/spi.v
set_global_assignment -name VHDL_FILE src/sdram.vhd set_global_assignment -name VHDL_FILE src/sdram.vhd
set_global_assignment -name VERILOG_FILE src/clock.v set_global_assignment -name VERILOG_FILE src/clock.v
set_global_assignment -name VHDL_FILE src/tsconf.vhd set_global_assignment -name VERILOG_FILE src/tsconf.v
set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv set_global_assignment -name SYSTEMVERILOG_FILE ddram.sv
set_global_assignment -name VERILOG_FILE dpram.v set_global_assignment -name VERILOG_FILE dpram.v
set_global_assignment -name SYSTEMVERILOG_FILE TSConf.svset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name SYSTEMVERILOG_FILE TSConf.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

1000
src/tsconf.v Normal file
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1553
src/tsconf.vhd
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