uzix/TSConf_MiST
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Adjust the timings.

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sorgelig
2020-05-12 20:07:47 +08:00
parent c08d8479be
commit 371f9984db
4 changed files with 55 additions and 34 deletions
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13
TSConf.sdc Normal file
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@ -0,0 +1,13 @@
derive_pll_clocks
derive_clock_uncertainty
set_multicycle_path -to {emu|tsconf|U16|*} -setup 2
set_multicycle_path -to {emu|tsconf|U16|*} -hold 1
set_multicycle_path -from {emu|tsconf|CPU|*} -setup 2
set_multicycle_path -from {emu|tsconf|CPU|*} -hold 1
set_multicycle_path -to {emu|tsconf|CPU|*} -setup 2
set_multicycle_path -to {emu|tsconf|CPU|*} -hold 1
set_multicycle_path -to {emu|tsconf|U15|*} -setup 2
set_multicycle_path -to {emu|tsconf|U15|*} -hold 1

1
files.qip
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@ -32,4 +32,5 @@ set_global_assignment -name VERILOG_FILE rtl/kempston_mouse.v
set_global_assignment -name VERILOG_FILE rtl/spi.v
set_global_assignment -name VERILOG_FILE rtl/clock.v
set_global_assignment -name VERILOG_FILE rtl/tsconf.v
set_global_assignment -name SDC_FILE TSConf.sdc
set_global_assignment -name SYSTEMVERILOG_FILE TSConf.sv

71
rtl/memory/sdram.v
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@ -43,70 +43,77 @@ always @(posedge clk) begin
reg rd;
reg [8:0] col;
reg [1:0] dqm;
reg [15:0] data;
reg [23:0] Ar;
reg rq;
SDRAM_DQ <= 16'hZZZZ;
sdr_cmd <= SdrCmd_xx;
data <= SDRAM_DQ;
SDRAM_DQ <= 16'bZ;
state <= state + 1'd1;
case (state)
// Init
'h00: begin
0: begin
sdr_cmd <= SdrCmd_pr; // PRECHARGE
SDRAM_A <= 0;
SDRAM_BA <= 0;
state <= state + 1'd1;
end
// REFRESH
'h03, 'h0A: begin
3,10: begin
sdr_cmd <= SdrCmd_re;
state <= state + 1'd1;
end
// LOAD MODE REGISTER
'h11: begin
17: begin
sdr_cmd <= SdrCmd_ms;
SDRAM_A <= {3'b000, 1'b1, 2'b00, 3'b010, 1'b0, 3'b000};
state <= state + 1'd1;
end
// Idle
'h18: begin
rd <= 0;
24: begin
if (rd) begin
DO <= SDRAM_DQ;
if (curr_cpu) DO_cpu <= SDRAM_DQ;
DO <= data;
if (curr_cpu) DO_cpu <= data;
end
state <= state;
Ar <= A;
dqm <= RNW ? 2'b00 : ~bsel;
rd <= 0;
if(cyc) begin
if (REQ) begin
sdr_cmd <= SdrCmd_ac; // ACTIVE
{SDRAM_A,SDRAM_BA,col} <= A;
dqm <= RNW ? 2'b00 : ~bsel;
rd <= RNW;
state <= state + 1'd1;
end else begin
sdr_cmd <= SdrCmd_re; // REFRESH
state <= 'h13;
end
rq <= REQ;
rd <= REQ & RNW;
state <= state + 1'd1;
end
end
// Start
25: begin
if (rq) begin
{SDRAM_A,SDRAM_BA,col} <= Ar;
sdr_cmd <= SdrCmd_ac;
end else begin
sdr_cmd <= SdrCmd_re;
state <= 19;
end
end
// Single read/write - with auto precharge
'h1A: begin
SDRAM_A <= {dqm, 2'b10, col}; // A10 = 1 enable auto precharge; A9..0 = column
state <= 'h16;
if (rd) sdr_cmd <= SdrCmd_rd; // READ
27: begin
SDRAM_A <= {dqm, 2'b10, col};
state <= 21;
if (rd) sdr_cmd <= SdrCmd_rd;
else begin
sdr_cmd <= SdrCmd_wr; // WRITE
sdr_cmd <= SdrCmd_wr;
SDRAM_DQ <= DI;
state <= 22;
end
end
// NOP
default:
begin
sdr_cmd <= SdrCmd_xx;
state <= state + 1'd1;
end
endcase
end

2
rtl/tsconf.v
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@ -747,7 +747,7 @@ wire wait_start_gluclock;
wire [7:0] mc146818a_do_bus;
reg ena_0_4375mhz;
always @(negedge clk_28mhz) begin
always @(posedge clk_28mhz) begin
reg [5:0] div;
div <= div + 1'd1;
ena_0_4375mhz <= !div; //28MHz/64