Adjust the timings.

TSConf.sdc

@@ -0,0 +1,13 @@
+derive_pll_clocks
+derive_clock_uncertainty
+
+set_multicycle_path -to {emu|tsconf|U16|*} -setup 2
+set_multicycle_path -to {emu|tsconf|U16|*} -hold 1
+
+set_multicycle_path -from {emu|tsconf|CPU|*} -setup 2
+set_multicycle_path -from {emu|tsconf|CPU|*} -hold 1
+set_multicycle_path -to {emu|tsconf|CPU|*} -setup 2
+set_multicycle_path -to {emu|tsconf|CPU|*} -hold 1
+
+set_multicycle_path -to {emu|tsconf|U15|*} -setup 2
+set_multicycle_path -to {emu|tsconf|U15|*} -hold 1

files.qip

@@ -32,4 +32,5 @@ set_global_assignment -name VERILOG_FILE rtl/kempston_mouse.v
 set_global_assignment -name VERILOG_FILE rtl/spi.v
 set_global_assignment -name VERILOG_FILE rtl/clock.v
 set_global_assignment -name VERILOG_FILE rtl/tsconf.v
+set_global_assignment -name SDC_FILE TSConf.sdc
 set_global_assignment -name SYSTEMVERILOG_FILE TSConf.sv

rtl/memory/sdram.v

@@ -43,70 +43,77 @@ always @(posedge clk) begin
 	reg        rd;
 	reg  [8:0] col;
 	reg  [1:0] dqm;
+	reg [15:0] data;
+	reg [23:0] Ar;
+	reg        rq;
 
-	SDRAM_DQ <= 16'hZZZZ;
+	sdr_cmd <= SdrCmd_xx;
+	data <= SDRAM_DQ;
+	SDRAM_DQ <= 16'bZ;
+	state <= state + 1'd1;
 
 	case (state)
 
 	// Init
-	'h00:	begin
+	0:	begin
 			sdr_cmd <= SdrCmd_pr;		// PRECHARGE
 			SDRAM_A <= 0;
 			SDRAM_BA <= 0;
-			state <= state + 1'd1;
 		end
 
 	// REFRESH
-	'h03, 'h0A: begin
+	3,10: begin
 			sdr_cmd <= SdrCmd_re;
-			state <= state + 1'd1;
 		end
 
 	// LOAD MODE REGISTER
-	'h11: begin
+	17: begin
 			sdr_cmd <= SdrCmd_ms;
 			SDRAM_A <= {3'b000, 1'b1, 2'b00, 3'b010, 1'b0, 3'b000};
-			state <= state + 1'd1;
 		end
 
 	// Idle
-	'h18: begin
+	24: begin
-			rd <= 0;
 			if (rd) begin
-				DO <= SDRAM_DQ;
+				DO <= data;
-				if (curr_cpu) DO_cpu <= SDRAM_DQ;
+				if (curr_cpu) DO_cpu <= data;
 			end
-			if(cyc) begin
+
-				if (REQ) begin
+			state <= state;
-					sdr_cmd <= SdrCmd_ac;	// ACTIVE
+			Ar <= A;
-					{SDRAM_A,SDRAM_BA,col} <= A;
 			dqm <= RNW ? 2'b00 : ~bsel;
-					rd <= RNW;
+			rd <= 0;
+
+			if(cyc) begin
+				rq <= REQ;
+				rd <= REQ & RNW;
 				state <= state + 1'd1;
-				end else begin
-					sdr_cmd <= SdrCmd_re;	// REFRESH
-					state <= 'h13;
 			end
 		end
+
+	// Start
+	25: begin
+			if (rq) begin
+				{SDRAM_A,SDRAM_BA,col} <= Ar;
+				sdr_cmd <= SdrCmd_ac;
+			end else begin
+				sdr_cmd <= SdrCmd_re;
+				state <= 19;
+			end
 		end
 
 	// Single read/write - with auto precharge
-	'h1A: begin
+	27: begin
-			SDRAM_A <= {dqm, 2'b10, col};	// A10 = 1 enable auto precharge; A9..0 = column
+			SDRAM_A <= {dqm, 2'b10, col};
-			state <= 'h16;
+			state <= 21;
-			if (rd) sdr_cmd <= SdrCmd_rd;	// READ
+			if (rd) sdr_cmd <= SdrCmd_rd;
 			else begin
-				sdr_cmd <= SdrCmd_wr;		// WRITE
+				sdr_cmd <= SdrCmd_wr;
 				SDRAM_DQ <= DI;
+				state <= 22;
 			end
 		end
 
-	// NOP
-	default:
-		begin
-			sdr_cmd <= SdrCmd_xx;
-			state <= state + 1'd1;
-		end
 	endcase
 end
 

rtl/tsconf.v

@@ -747,7 +747,7 @@ wire       wait_start_gluclock;
 wire [7:0] mc146818a_do_bus;
 
 reg ena_0_4375mhz;
-always @(negedge clk_28mhz) begin
+always @(posedge clk_28mhz) begin
 	reg [5:0] div;
 	div <= div + 1'd1;
 	ena_0_4375mhz <= !div; //28MHz/64