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https://github.com/UzixLS/TSConf_MiST.git
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update tsconf to commit 83afbba6f5d366f96297028aa3d64512fa254a51
This commit is contained in:
Eugene Lozovoy
321
rtl/z80/zmem.v
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321
rtl/z80/zmem.v
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`include "tune.v"
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// PentEvo project (c) NedoPC 2008-2009
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//
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// Z80 memory manager: routes ROM/RAM accesses, makes wait-states for 14MHz or stall condition, etc.
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//
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//
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// clk _/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\
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// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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// zclk /```\___/```\___/```\___/```````\_______/```````\_______/```````````````\_______________/```````````````\_______________/`
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// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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// zpos `\___/```\___/```\___/```\___________/```\___________/```\___________________________/```\___________________________/```\
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// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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// zneg _/```\___/```\___/```\_______/```\___________/```\___________________/```\___________________________/```\________________
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module zmem
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(
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input wire clk,
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input wire c1, c2, c3,
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input wire zneg, // strobes which show positive and negative edges of zclk
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// Z80
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input wire rst,
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input wire [15:0] za,
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output wire [ 7:0] zd_out, // output to Z80 bus
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output wire zd_ena, // output to Z80 bus enable
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input wire opfetch,
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input wire opfetch_s,
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input wire memrd,
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input wire memwr,
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input wire memwr_s,
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input wire [ 1:0] turbo, // 2'b00 - 3.5,
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// 2'b01 - 7.0,
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// 2'b1x - 14.0
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input wire [3:0] cache_en,
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input wire [3:0] memconf,
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input wire [31:0] xt_page,
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output wire [4:0] rompg,
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output wire csrom,
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output wire romoe_n,
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output wire romwe_n,
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output wire dos,
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output wire dos_on,
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output wire dos_off,
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output wire vdos,
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output reg pre_vdos,
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input wire vdos_on,
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input wire vdos_off,
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// DRAM
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output wire cpu_req,
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output wire [20:0] cpu_addr,
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output wire cpu_wrbsel,
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input wire [15:0] cpu_rddata,
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input wire cpu_next,
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input wire cpu_strobe,
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input wire cpu_latch,
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output wire cpu_stall // for zclock
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);
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// controls
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wire rom128 = memconf[0];
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wire w0_we = memconf[1];
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wire w0_map_n = memconf[2];
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wire w0_ram = memconf[3];
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// pager
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wire [7:0] xtpage[0:3];
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assign xtpage[0] = vdos ? 8'hFF : {xt_page[7:2], w0_map_n ? xt_page[1:0] : {~dos, rom128}};
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assign xtpage[1] = xt_page[15:8];
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assign xtpage[2] = xt_page[23:16];
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assign xtpage[3] = xt_page[31:24];
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wire [1:0] win = za[15:14];
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wire win0 = ~|win;
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wire ramwr_en = !win0 || w0_we || vdos;
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wire rom_n_ram = win0 && !w0_ram && !vdos;
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wire [7:0] page = xtpage[win];
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// DOS signal control
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reg dos_r;
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assign dos_on = win0 && opfetch_s && (za[13:8]==6'h3D) && rom128 && !w0_map_n;
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assign dos_off = !win0 && opfetch_s && !vdos;
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assign dos = (dos_on || dos_off) ^^ dos_r; // to make dos appear 1 clock earlier than dos_r
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always @(posedge clk)
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if (rst)
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dos_r <= 1'b0;
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else if (dos_off)
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dos_r <= 1'b0;
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else if (dos_on)
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dos_r <= 1'b1;
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// VDOS signal control
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// vdos switching is delayed till next opfetch due to INIR that writes right after iord cycle
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reg vdos_r;
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assign vdos = opfetch ? pre_vdos : vdos_r; // vdos appears as soon as first opfetch
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always @(posedge clk)
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if (rst || vdos_off)
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begin
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pre_vdos <= 1'b0;
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vdos_r <= 1'b0;
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end
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else if (vdos_on)
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pre_vdos <= 1'b1;
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else if (opfetch_s)
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vdos_r <= pre_vdos;
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// RAM
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wire cache_hit_en;
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assign zd_ena = !rom_n_ram && memrd;
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wire ramreq = ((memrd && !cache_hit_en) || (memwr && ramwr_en));
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// address, data in and data out
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wire [15:0] cache_d;
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wire cache_v;
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assign cpu_wrbsel = za[0];
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assign cpu_addr[20:0] = {page, za[13:1]};
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wire [15:0] mem_d = cpu_latch ? cpu_rddata : cache_d;
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assign zd_out = ~cpu_wrbsel ? mem_d[7:0] : mem_d[15:8];
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// Z80 controls
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// 7/3.5MHz support
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reg ramreq_r;
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reg pre_ramreq_r;
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reg pending_cpu_req;
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reg stall14_cycrd;
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reg stall14_fin;
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wire dram_beg = ramreq && !pre_ramreq_r && zneg;
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wire cpureq_357 = ramreq && !ramreq_r;
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wire cpureq_14 = dram_beg || pending_cpu_req;
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wire stall357 = cpureq_357 && !cpu_next;
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wire stall14_ini = dram_beg && (!cpu_next || opfetch || memrd); // no wait at all in write cycles, if next dram cycle is available
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wire stall14_cyc = memrd ? stall14_cycrd : !cpu_next;
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wire stall14 = stall14_ini || stall14_cyc || stall14_fin;
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wire turbo14 = turbo[1];
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assign cpu_req = turbo14 ? cpureq_14 : cpureq_357;
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assign cpu_stall = turbo14 ? stall14 : stall357;
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// 14MHz support
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// wait tables:
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//
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// M1 opcode fetch, dram_beg concurs with:
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// c3: +3
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// c2: +4
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// c1: +5
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// c0: +6
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//
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// memory read, dram_beg concurs with:
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// c3: +2
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// c2: +3
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// c1: +4
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// c0: +5
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//
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// memory write: no wait
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//
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// special case: if dram_beg pulses 1 when cpu_next is 0,
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// unconditional wait has to be performed until cpu_next is 1, and
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// then wait as if dram_beg would concur with c0
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// memrd, opfetch - wait till c3 && cpu_next,
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// memwr - wait till cpu_next
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always @(posedge clk)
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if (c3 && !cpu_stall)
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ramreq_r <= ramreq;
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always @(posedge clk)
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if (zneg)
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pre_ramreq_r <= ramreq;
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always @(posedge clk)
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if (rst)
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pending_cpu_req <= 1'b0;
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else if (cpu_next && c3)
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pending_cpu_req <= 1'b0;
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else if (dram_beg)
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pending_cpu_req <= 1'b1;
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always @(posedge clk)
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if (rst)
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stall14_cycrd <= 1'b0;
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else if (cpu_next && c3)
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stall14_cycrd <= 1'b0;
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else if (dram_beg && (!c3 || !cpu_next) && (opfetch || memrd))
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stall14_cycrd <= 1'b1;
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always @(posedge clk)
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if (rst)
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stall14_fin <= 1'b0;
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else if (stall14_fin && ((opfetch && c1) || (memrd && c2)))
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stall14_fin <= 1'b0;
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else if (cpu_next && c3 && cpu_req && (opfetch || memrd))
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stall14_fin <= 1'b1;
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// cache
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wire [12:0] cache_a;
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wire [12:0] cpu_hi_addr = {page[7:0], za[13:9]};
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// wire cache_hit = (ch_addr[7:2] != 6'b011100) && (cpu_hi_addr == cache_a) && cache_v; // debug for BM
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wire cache_hit = (cpu_hi_addr == cache_a) && cache_v; // asynchronous signal meaning that address requested by CPU is cached and valid
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assign cache_hit_en = cache_hit && cache_en[win];
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wire cache_inv = cache_hit && memwr_s && ramwr_en; // cache invalidation should be only performed if write happens to cached address
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wire [7:0] ch_addr = cpu_addr[7:0];
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// wire [14:0] cpu_hi_addr = {page[7:0], za[13:7]};
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// wire [14:0] cache_a;
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// wire [7:0] ch_addr = {2'b0, cpu_addr[5:0]};
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dpram #(.DATAWIDTH(16), .ADDRWIDTH(8)) cache_data
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(
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.clock(clk),
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.address_a(ch_addr),
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.data_a(cpu_rddata),
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.wren_a(cpu_strobe),
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.address_b(ch_addr),
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.q_b(cache_d)
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);
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dpram #(.DATAWIDTH(14), .ADDRWIDTH(8)) cache_addr
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(
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.clock(clk),
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.address_a(ch_addr),
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.data_a({!cache_inv, cpu_hi_addr}),
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.wren_a(cpu_strobe || cache_inv),
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.address_b(ch_addr),
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.q_b({cache_v, cache_a})
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);
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/*
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altdpram cache_data
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(
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.inclock (clk),
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.outclock (clk),
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.data (cpu_rddata),
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.rdaddress (ch_addr),
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.wraddress (ch_addr),
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.wren (cpu_strobe),
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.q (cache_d),
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.aclr (1'b0),
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.byteena (1'b1),
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.inclocken (1'b1),
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.outclocken (1'b1),
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.rdaddressstall (1'b0),
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.rden (1'b1),
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.wraddressstall (1'b0)
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);
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defparam
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cache_data.indata_aclr = "OFF",
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cache_data.indata_reg = "INCLOCK",
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cache_data.intended_device_family = "ACEX1K",
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cache_data.lpm_type = "altdpram",
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cache_data.outdata_aclr = "OFF",
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cache_data.outdata_reg = "OUTCLOCK",
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cache_data.rdaddress_aclr = "OFF",
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cache_data.rdaddress_reg = "UNREGISTERED",
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cache_data.rdcontrol_aclr = "OFF",
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cache_data.rdcontrol_reg = "UNREGISTERED",
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cache_data.width = 16,
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cache_data.widthad = 8,
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cache_data.wraddress_aclr = "OFF",
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cache_data.wraddress_reg = "INCLOCK",
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cache_data.wrcontrol_aclr = "OFF",
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cache_data.wrcontrol_reg = "INCLOCK";
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altdpram cache_addr
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(
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.inclock (clk),
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.outclock (clk),
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.data ({!cache_inv, cpu_hi_addr}),
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.rdaddress (ch_addr),
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.wraddress (ch_addr),
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.wren (cpu_strobe || cache_inv),
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.q ({cache_v, cache_a}),
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.aclr (1'b0),
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.byteena (1'b1),
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.inclocken (1'b1),
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.outclocken (1'b1),
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.rdaddressstall (1'b0),
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.rden (1'b1),
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.wraddressstall (1'b0)
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);
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defparam
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cache_addr.indata_aclr = "OFF",
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cache_addr.indata_reg = "INCLOCK",
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cache_addr.intended_device_family = "ACEX1K",
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cache_addr.lpm_type = "altdpram",
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cache_addr.outdata_aclr = "OFF",
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cache_addr.outdata_reg = "OUTCLOCK",
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cache_addr.rdaddress_aclr = "OFF",
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cache_addr.rdaddress_reg = "UNREGISTERED",
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cache_addr.rdcontrol_aclr = "OFF",
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cache_addr.rdcontrol_reg = "UNREGISTERED",
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cache_addr.width = 14,
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cache_addr.widthad = 8,
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cache_addr.wraddress_aclr = "OFF",
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cache_addr.wraddress_reg = "INCLOCK",
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cache_addr.wrcontrol_aclr = "OFF",
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cache_addr.wrcontrol_reg = "INCLOCK";
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*/
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// ROM chip
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assign csrom = rom_n_ram;
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assign romoe_n = !memrd;
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assign romwe_n = !(memwr && w0_we);
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assign rompg = xtpage[0][4:0];
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endmodule
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