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update tsconf to commit 83afbba6f5d366f96297028aa3d64512fa254a51
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@ -1,33 +1,35 @@
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// This module fetches video data from DRAM
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// This module fetches video data from DRAM
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`include "tune.v"
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module video_fetch
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(
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// clocks
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input wire clk,
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// control
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input wire [3:0] f_sel,
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input wire [1:0] b_sel,
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input wire fetch_stb,
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// video data
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output reg [31:0] fetch_data,
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output reg [31:0] fetch_temp,
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// DRAM interface
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input wire video_strobe,
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input wire [15:0] video_data
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);
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// fetching data
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always @(posedge clk) if (video_strobe)
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begin
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if (f_sel[0]) fetch_temp[ 7: 0] <= b_sel[0] ? video_data[15:8] : video_data[ 7:0];
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if (f_sel[1]) fetch_temp[15: 8] <= b_sel[1] ? video_data[15:8] : video_data[ 7:0];
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if (f_sel[2]) fetch_temp[23:16] <= video_data[ 7:0];
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if (f_sel[3]) fetch_temp[31:24] <= video_data[15:8];
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end
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always @(posedge clk) if (fetch_stb) fetch_data <= fetch_temp;
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(
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// clocks
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input wire clk,
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// control
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input wire [3:0] f_sel,
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input wire [1:0] b_sel,
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input wire fetch_stb,
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// video data
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output reg [31:0] fetch_data,
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output reg [31:0] fetch_temp,
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// DRAM interface
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input wire video_strobe,
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input wire [15:0] video_data
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);
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always @(posedge clk) if (video_strobe)
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begin
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if (f_sel[0]) fetch_temp[ 7: 0] <= b_sel[0] ? video_data[15:8] : video_data[ 7:0];
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if (f_sel[1]) fetch_temp[15: 8] <= b_sel[1] ? video_data[15:8] : video_data[ 7:0];
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if (f_sel[2]) fetch_temp[23:16] <= video_data[ 7:0];
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if (f_sel[3]) fetch_temp[31:24] <= video_data[15:8];
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end
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always @(posedge clk) if (fetch_stb)
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fetch_data <= fetch_temp;
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endmodule
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