mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 23:01:37 +03:00
update tsconf to commit 83afbba6f5d366f96297028aa3d64512fa254a51
This commit is contained in:
Eugene Lozovoy
BIN
rtl/periph/CMOS.bin
Normal file
BIN
rtl/periph/CMOS.bin
Normal file
Binary file not shown.
21
rtl/periph/CMOS.mif
Normal file
21
rtl/periph/CMOS.mif
Normal file
@ -0,0 +1,21 @@
|
||||
-- http://srecord.sourceforge.net/
|
||||
--
|
||||
-- Generated automatically by srec_cat -o --mif
|
||||
--
|
||||
DEPTH = 256;
|
||||
WIDTH = 8;
|
||||
ADDRESS_RADIX = HEX;
|
||||
DATA_RADIX = HEX;
|
||||
CONTENT BEGIN
|
||||
0000: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 AA 00 00 00 00 00 00;
|
||||
0018: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
|
||||
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
|
||||
0048: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
|
||||
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
|
||||
0078: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
|
||||
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
|
||||
00A8: 00 00 00 00 00 00 00 00 00 00 00 01 03 00 00 02 01 00 00 00 02 00 00 00;
|
||||
00C0: 00 00 00 00 00 00 00 00 42 08 84 10 C6 18 08 21 4A 29 8C 31 CE 39 21 04;
|
||||
00D8: 63 0C A5 14 E7 1C 29 25 6B 2D AD 35 EF 3D 78 7B 00 00 00 00 00 00 00 00;
|
||||
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
|
||||
END;
|
||||
66
rtl/periph/kempston_mouse.v
Normal file
66
rtl/periph/kempston_mouse.v
Normal file
@ -0,0 +1,66 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// PS2-to-Kempston Mouse v2
|
||||
// (C) 2017,2018 Sorgelig
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module kempston_mouse
|
||||
(
|
||||
input clk_sys,
|
||||
input reset,
|
||||
|
||||
input [24:0] ps2_mouse,
|
||||
|
||||
input [2:0] addr,
|
||||
output sel,
|
||||
output [7:0] dout
|
||||
);
|
||||
|
||||
assign dout = data;
|
||||
assign sel = port_sel;
|
||||
|
||||
reg [11:0] dx;
|
||||
reg [11:0] dy;
|
||||
|
||||
reg [7:0] data;
|
||||
reg port_sel;
|
||||
always @* begin
|
||||
port_sel = 1;
|
||||
casex(addr)
|
||||
3'b011: data = dx[7:0];
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||||
3'b111: data = dy[7:0];
|
||||
3'bX10: data = ~{5'b00000,ps2_mouse[2], ps2_mouse[0], ps2_mouse[1]} ;
|
||||
default: {port_sel,data} = 8'hFF;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
reg old_status;
|
||||
old_status <= ps2_mouse[24];
|
||||
|
||||
if(reset) begin
|
||||
dx <= 128; // dx != dy for better mouse detection
|
||||
dy <= 0;
|
||||
end
|
||||
else if(old_status != ps2_mouse[24]) begin
|
||||
dx <= dx + {{4{ps2_mouse[4]}},ps2_mouse[15:8]};
|
||||
dy <= dy + {{4{ps2_mouse[5]}},ps2_mouse[23:16]};
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
170
rtl/periph/keyboard.vhd
Normal file
170
rtl/periph/keyboard.vhd
Normal file
@ -0,0 +1,170 @@
|
||||
-------------------------------------------------------------------[28.07.2014]
|
||||
-- KEYBOARD CONTROLLER USB HID scancode to Spectrum matrix conversion
|
||||
-------------------------------------------------------------------------------
|
||||
-- V0.1 05.10.2011 первая версия
|
||||
-- V0.2 16.03.2014 измененмия в key_f (активная клавиша теперь устанавливается в '1')
|
||||
-- V1.0 24.07.2014 доработан под USB HID Keyboard
|
||||
-- V1.1 28.07.2014 добавлены спец клавиши
|
||||
-- WXEDA 10.03.2015 добавлен контроллер ps/2
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity keyboard is
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
RESET : in std_logic;
|
||||
A : in std_logic_vector(7 downto 0);
|
||||
KEYB : out std_logic_vector(4 downto 0);
|
||||
KEY_RESET: out std_logic;
|
||||
SCANCODE : out std_logic_vector(7 downto 0);
|
||||
PS2_KEY : in std_logic_vector(10 downto 0)
|
||||
);
|
||||
end keyboard;
|
||||
|
||||
architecture rtl of keyboard is
|
||||
|
||||
-- Internal signals
|
||||
type key_matrix is array (7 downto 0) of std_logic_vector(4 downto 0);
|
||||
signal keys : key_matrix;
|
||||
signal row0, row1, row2, row3, row4, row5, row6, row7 : std_logic_vector(4 downto 0);
|
||||
signal flg : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- Output addressed row to ULA
|
||||
row0 <= keys(0) when A(0) = '0' else (others => '1');
|
||||
row1 <= keys(1) when A(1) = '0' else (others => '1');
|
||||
row2 <= keys(2) when A(2) = '0' else (others => '1');
|
||||
row3 <= keys(3) when A(3) = '0' else (others => '1');
|
||||
row4 <= keys(4) when A(4) = '0' else (others => '1');
|
||||
row5 <= keys(5) when A(5) = '0' else (others => '1');
|
||||
row6 <= keys(6) when A(6) = '0' else (others => '1');
|
||||
row7 <= keys(7) when A(7) = '0' else (others => '1');
|
||||
KEYB <= row0 and row1 and row2 and row3 and row4 and row5 and row6 and row7;
|
||||
|
||||
process (CLK) begin
|
||||
if rising_edge(CLK) then
|
||||
flg <= ps2_key(10);
|
||||
|
||||
if RESET = '1' then
|
||||
keys(0) <= (others => '1');
|
||||
keys(1) <= (others => '1');
|
||||
keys(2) <= (others => '1');
|
||||
keys(3) <= (others => '1');
|
||||
keys(4) <= (others => '1');
|
||||
keys(5) <= (others => '1');
|
||||
keys(6) <= (others => '1');
|
||||
keys(7) <= (others => '1');
|
||||
KEY_RESET <= '0';
|
||||
SCANCODE <= (others => '0');
|
||||
else
|
||||
if flg /= ps2_key(10) then
|
||||
if (ps2_key(9) = '1') then
|
||||
SCANCODE <= ps2_key(7 downto 0);
|
||||
else
|
||||
SCANCODE <= (others => '1');
|
||||
end if;
|
||||
|
||||
case ps2_key(7 downto 0) is
|
||||
when X"12" => keys(0)(0) <= not ps2_key(9); -- Left shift (CAPS SHIFT)
|
||||
when X"59" => keys(0)(0) <= not ps2_key(9); -- Right shift (CAPS SHIFT)
|
||||
when X"1a" => keys(0)(1) <= not ps2_key(9); -- Z
|
||||
when X"22" => keys(0)(2) <= not ps2_key(9); -- X
|
||||
when X"21" => keys(0)(3) <= not ps2_key(9); -- C
|
||||
when X"2a" => keys(0)(4) <= not ps2_key(9); -- V
|
||||
|
||||
when X"1c" => keys(1)(0) <= not ps2_key(9); -- A
|
||||
when X"1b" => keys(1)(1) <= not ps2_key(9); -- S
|
||||
when X"23" => keys(1)(2) <= not ps2_key(9); -- D
|
||||
when X"2b" => keys(1)(3) <= not ps2_key(9); -- F
|
||||
when X"34" => keys(1)(4) <= not ps2_key(9); -- G
|
||||
|
||||
when X"15" => keys(2)(0) <= not ps2_key(9); -- Q
|
||||
when X"1d" => keys(2)(1) <= not ps2_key(9); -- W
|
||||
when X"24" => keys(2)(2) <= not ps2_key(9); -- E
|
||||
when X"2d" => keys(2)(3) <= not ps2_key(9); -- R
|
||||
when X"2c" => keys(2)(4) <= not ps2_key(9); -- T
|
||||
|
||||
when X"16" => keys(3)(0) <= not ps2_key(9); -- 1
|
||||
when X"1e" => keys(3)(1) <= not ps2_key(9); -- 2
|
||||
when X"26" => keys(3)(2) <= not ps2_key(9); -- 3
|
||||
when X"25" => keys(3)(3) <= not ps2_key(9); -- 4
|
||||
when X"2e" => keys(3)(4) <= not ps2_key(9); -- 5
|
||||
|
||||
when X"45" => keys(4)(0) <= not ps2_key(9); -- 0
|
||||
when X"46" => keys(4)(1) <= not ps2_key(9); -- 9
|
||||
when X"3e" => keys(4)(2) <= not ps2_key(9); -- 8
|
||||
when X"3d" => keys(4)(3) <= not ps2_key(9); -- 7
|
||||
when X"36" => keys(4)(4) <= not ps2_key(9); -- 6
|
||||
|
||||
when X"4d" => keys(5)(0) <= not ps2_key(9); -- P
|
||||
when X"44" => keys(5)(1) <= not ps2_key(9); -- O
|
||||
when X"43" => keys(5)(2) <= not ps2_key(9); -- I
|
||||
when X"3c" => keys(5)(3) <= not ps2_key(9); -- U
|
||||
when X"35" => keys(5)(4) <= not ps2_key(9); -- Y
|
||||
|
||||
when X"5a" => keys(6)(0) <= not ps2_key(9); -- ENTER
|
||||
when X"4b" => keys(6)(1) <= not ps2_key(9); -- L
|
||||
when X"42" => keys(6)(2) <= not ps2_key(9); -- K
|
||||
when X"3b" => keys(6)(3) <= not ps2_key(9); -- J
|
||||
when X"33" => keys(6)(4) <= not ps2_key(9); -- H
|
||||
|
||||
when X"29" => keys(7)(0) <= not ps2_key(9); -- SPACE
|
||||
when X"14" => keys(7)(1) <= not ps2_key(9); -- CTRL (Symbol Shift)
|
||||
when X"3a" => keys(7)(2) <= not ps2_key(9); -- M
|
||||
when X"31" => keys(7)(3) <= not ps2_key(9); -- N
|
||||
when X"32" => keys(7)(4) <= not ps2_key(9); -- B
|
||||
|
||||
-- Cursor keys
|
||||
when X"6b" => keys(0)(0) <= not ps2_key(9); -- Left (CAPS 5)
|
||||
keys(3)(4) <= not ps2_key(9);
|
||||
when X"72" => keys(0)(0) <= not ps2_key(9); -- Down (CAPS 6)
|
||||
keys(4)(4) <= not ps2_key(9);
|
||||
when X"75" => keys(0)(0) <= not ps2_key(9); -- Up (CAPS 7)
|
||||
keys(4)(3) <= not ps2_key(9);
|
||||
when X"74" => keys(0)(0) <= not ps2_key(9); -- Right (CAPS 8)
|
||||
keys(4)(2) <= not ps2_key(9);
|
||||
|
||||
-- Other special keys sent to the ULA as key combinations
|
||||
when X"66" => keys(0)(0) <= not ps2_key(9); -- Backspace (CAPS 0)
|
||||
keys(4)(0) <= not ps2_key(9);
|
||||
when X"58" => keys(0)(0) <= not ps2_key(9); -- Caps lock (CAPS 2)
|
||||
keys(3)(1) <= not ps2_key(9);
|
||||
when X"0d" => keys(0)(0) <= not ps2_key(9); -- Tab (CAPS SPACE)
|
||||
keys(7)(0) <= not ps2_key(9);
|
||||
when X"49" => keys(7)(2) <= not ps2_key(9); -- .
|
||||
keys(7)(1) <= not ps2_key(9);
|
||||
when X"4e" => keys(6)(3) <= not ps2_key(9); -- -
|
||||
keys(7)(1) <= not ps2_key(9);
|
||||
when X"0e" => keys(3)(0) <= not ps2_key(9); -- ` (EDIT)
|
||||
keys(0)(0) <= not ps2_key(9);
|
||||
when X"41" => keys(7)(3) <= not ps2_key(9); -- ,
|
||||
keys(7)(1) <= not ps2_key(9);
|
||||
when X"4c" => keys(5)(1) <= not ps2_key(9); -- ;
|
||||
keys(7)(1) <= not ps2_key(9);
|
||||
when X"52" => keys(5)(0) <= not ps2_key(9); -- "
|
||||
keys(7)(1) <= not ps2_key(9);
|
||||
when X"5d" => keys(0)(1) <= not ps2_key(9); -- :
|
||||
keys(7)(1) <= not ps2_key(9);
|
||||
when X"55" => keys(6)(1) <= not ps2_key(9); -- =
|
||||
keys(7)(1) <= not ps2_key(9);
|
||||
when X"54" => keys(4)(2) <= not ps2_key(9); -- (
|
||||
keys(7)(1) <= not ps2_key(9);
|
||||
when X"5b" => keys(4)(1) <= not ps2_key(9); -- )
|
||||
keys(7)(1) <= not ps2_key(9);
|
||||
when X"4a" => keys(0)(3) <= not ps2_key(9); -- ?
|
||||
keys(7)(1) <= not ps2_key(9);
|
||||
--------------------------------------------
|
||||
|
||||
when X"78" => KEY_RESET <= ps2_key(9); -- F11
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
245
rtl/periph/mc146818a.v
Normal file
245
rtl/periph/mc146818a.v
Normal file
@ -0,0 +1,245 @@
|
||||
//-----------------------------------------------------------------[18.10.2014]
|
||||
// MC146818A REAL-TIME CLOCK PLUS RAM
|
||||
//-----------------------------------------------------------------------------
|
||||
// V0.1 05.10.2011 Initial version
|
||||
// V0.2 06.09.2014 Added General Purpose RAM
|
||||
|
||||
module mc146818a
|
||||
(
|
||||
input RESET,
|
||||
input CLK,
|
||||
input ENA,
|
||||
input CS,
|
||||
|
||||
input [64:0] RTC,
|
||||
input [31:0] CMOSCfg,
|
||||
|
||||
input [7:0] KEYSCANCODE,
|
||||
input WR,
|
||||
input [7:0] A,
|
||||
input [7:0] DI,
|
||||
output [7:0] DO
|
||||
);
|
||||
|
||||
reg [18:0] pre_scaler =0;
|
||||
reg [1:0] leap_reg =0;
|
||||
reg [7:0] seconds_reg =0; // 00
|
||||
reg [7:0] seconds_alarm_reg =0; // 01
|
||||
reg [7:0] minutes_reg =0; // 02
|
||||
reg [7:0] minutes_alarm_reg = 0;// 03
|
||||
reg [7:0] hours_reg =0; // 04
|
||||
reg [7:0] hours_alarm_reg ='hff;// 05
|
||||
reg [7:0] weeks_reg = 1; // 06
|
||||
reg [7:0] days_reg = 1; // 07
|
||||
reg [7:0] month_reg = 1; // 08
|
||||
reg [7:0] year_reg = 0; // 09
|
||||
reg [7:0] a_reg; // 0A
|
||||
reg [7:0] b_reg = 8'b00000010; // 0B
|
||||
reg [7:0] c_reg; // 0C
|
||||
|
||||
wire [7:0] CMOS_Dout;
|
||||
reg [7:0] Dout;
|
||||
|
||||
assign DO = Dout;
|
||||
|
||||
always @(*) begin
|
||||
case (A[7:0])
|
||||
8'h00 : Dout <= seconds_reg;
|
||||
8'h01 : Dout <= seconds_alarm_reg;
|
||||
8'h02 : Dout <= minutes_reg;
|
||||
8'h03 : Dout <= minutes_alarm_reg;
|
||||
8'h04 : Dout <= hours_reg;
|
||||
8'h05 : Dout <= hours_alarm_reg;
|
||||
8'h06 : Dout <= weeks_reg;
|
||||
8'h07 : Dout <= days_reg;
|
||||
8'h08 : Dout <= month_reg;
|
||||
8'h09 : Dout <= year_reg;
|
||||
8'h0a : Dout <= a_reg;
|
||||
8'h0b : Dout <= b_reg;
|
||||
8'h0c : Dout <= c_reg;
|
||||
8'h0d : Dout <= 8'b10000000;
|
||||
|
||||
// 8'hb1 : Dout <= CMOSCfg[7:6]; // CPU Speed
|
||||
// 8'hb2 : Dout <= 0; // Boot device
|
||||
// 8'hb3 : Dout <= CMOSCfg[8]; // CPU Cache
|
||||
// 8'hb4 : Dout <= CMOSCfg[13:11]; // F11
|
||||
// 8'hb5 : Dout <= CMOSCfg[15:14]; // F11 bank
|
||||
// 8'hb6 : Dout <= CMOSCfg[18:16]; // Shift+F11
|
||||
// 8'hb7 : Dout <= CMOSCfg[20:19]; // Shift+F11 bank
|
||||
// 8'hb8 : Dout <= CMOSCfg[10:9]; // #7FFD
|
||||
// 8'hb9 : Dout <= CMOSCfg[23:21]; // ZX Palette
|
||||
// 8'hba : Dout <= CMOSCfg[24]; // NGS Reset
|
||||
// 8'hbb : Dout <= CMOSCfg[27:25]; // INT offset
|
||||
|
||||
8'hf0 : Dout <= KEYSCANCODE;
|
||||
default: Dout <= CMOS_Dout;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (RTC[62] && !b_reg[7]) begin
|
||||
seconds_reg <= RTC[7:0];
|
||||
minutes_reg <= RTC[15:8];
|
||||
hours_reg <= RTC[23:16];
|
||||
days_reg <= RTC[31:24];
|
||||
month_reg <= RTC[39:32];
|
||||
year_reg <= RTC[47:40];
|
||||
weeks_reg <= RTC[55:48] + 1'b1;
|
||||
b_reg <= 8'b00000010;
|
||||
end
|
||||
|
||||
if (RESET) b_reg <= 8'b00000010;
|
||||
else if (WR & CS) begin
|
||||
/*
|
||||
case (A[7:0])
|
||||
0 : seconds_reg <= DI;
|
||||
1 : seconds_alarm_reg <= DI;
|
||||
2 : minutes_reg <= DI;
|
||||
3 : minutes_alarm_reg <= DI;
|
||||
4 : hours_reg <= DI;
|
||||
5 : hours_alarm_reg <= DI;
|
||||
6 : weeks_reg <= DI;
|
||||
7 : days_reg <= DI;
|
||||
8 : month_reg <= DI;
|
||||
9 : year_reg <= DI;
|
||||
11 : begin
|
||||
b_reg <= DI;
|
||||
if (b_reg[2] == 1'b0) begin // BCD to BIN convertion
|
||||
if (DI[4] == 1'b0) leap_reg <= DI[1:0];
|
||||
else leap_reg <= {~DI[1], DI[0]};
|
||||
end
|
||||
else begin
|
||||
leap_reg <= DI[1:0];
|
||||
end
|
||||
end
|
||||
endcase
|
||||
*/
|
||||
end
|
||||
|
||||
if (RESET) begin
|
||||
a_reg <= 8'b00100110;
|
||||
c_reg <= 0;
|
||||
end
|
||||
else if (~b_reg[7] & ENA) begin
|
||||
if (pre_scaler) begin
|
||||
pre_scaler <= pre_scaler - 1'd1;
|
||||
a_reg[7] <= 0;
|
||||
end
|
||||
else begin
|
||||
pre_scaler <= 437500; //(0.4375MHz)
|
||||
a_reg[7] <= 1;
|
||||
c_reg[4] <= 1;
|
||||
// alarm
|
||||
if ((seconds_reg == seconds_alarm_reg) && (minutes_reg == minutes_alarm_reg) && (hours_reg == hours_alarm_reg)) c_reg[5] <= 1'b1;
|
||||
|
||||
if (~b_reg[2]) begin
|
||||
// DM binary-coded-decimal (BCD) data mode
|
||||
if (seconds_reg[3:0] != 9) seconds_reg[3:0] <= seconds_reg[3:0] + 1'd1;
|
||||
else begin
|
||||
seconds_reg[3:0] <= 0;
|
||||
if (seconds_reg[6:4] != 5) seconds_reg[6:4] <= seconds_reg[6:4] + 1'd1;
|
||||
else begin
|
||||
seconds_reg[6:4] <= 0;
|
||||
if (minutes_reg[3:0] != 9) minutes_reg[3:0] <= minutes_reg[3:0] + 1'd1;
|
||||
else begin
|
||||
minutes_reg[3:0] <= 0;
|
||||
if (minutes_reg[6:4] != 5) minutes_reg[6:4] <= minutes_reg[6:4] + 1'd1;
|
||||
else begin
|
||||
minutes_reg[6:4] <= 0;
|
||||
if (hours_reg[3:0] == 9) begin
|
||||
hours_reg[3:0] <= 0;
|
||||
hours_reg[5:4] <= hours_reg[5:4] + 1'd1;
|
||||
end
|
||||
else if ({b_reg[1], hours_reg[7], hours_reg[4:0]} == 7'b0010010) begin
|
||||
hours_reg[4:0] <= 1;
|
||||
hours_reg[7] <= ~hours_reg[7];
|
||||
end
|
||||
else if (({b_reg[1], hours_reg[7], hours_reg[4:0]} != 7'b0110010) &&
|
||||
({b_reg[1], hours_reg[5:0]} != 7'b1100011)) hours_reg[3:0] <= hours_reg[3:0] + 1'd1;
|
||||
else begin
|
||||
if (~b_reg[1]) hours_reg[7:0] <= 1;
|
||||
else hours_reg[5:0] <= 0;
|
||||
|
||||
if (weeks_reg[2:0] != 7) weeks_reg[2:0] <= weeks_reg[2:0] + 1'd1;
|
||||
else weeks_reg[2:0] <= 1;
|
||||
|
||||
if (({month_reg, days_reg, leap_reg} == {16'h0228, 2'b01}) ||
|
||||
({month_reg, days_reg, leap_reg} == {16'h0228, 2'b10}) ||
|
||||
({month_reg, days_reg, leap_reg} == {16'h0228, 2'b11}) ||
|
||||
({month_reg, days_reg, leap_reg} == {16'h0229, 2'b00}) ||
|
||||
({month_reg, days_reg} == 16'h0430) ||
|
||||
({month_reg, days_reg} == 16'h0630) ||
|
||||
({month_reg, days_reg} == 16'h0930) ||
|
||||
({month_reg, days_reg} == 16'h1130) ||
|
||||
(days_reg == 8'h31)) begin
|
||||
|
||||
days_reg[5:0] <= 1;
|
||||
if (month_reg[3:0] == 9) month_reg[4:0] <= 'h10;
|
||||
else if (month_reg[4:0] != 'h12) month_reg[3:0] <= month_reg[3:0] + 1'd1;
|
||||
else begin
|
||||
month_reg[4:0] <= 1;
|
||||
leap_reg[1:0] <= leap_reg[1:0] + 1'd1;
|
||||
if (year_reg[3:0] != 9) year_reg[3:0] <= year_reg[3:0] + 1'd1;
|
||||
else begin
|
||||
year_reg[3:0] <= 0;
|
||||
if (year_reg[7:4] != 9) year_reg[7:4] <= year_reg[7:4] + 1'd1;
|
||||
else year_reg[7:4] <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
else if (days_reg[3:0] != 9) days_reg[3:0] <= days_reg[3:0] + 1'd1;
|
||||
else begin
|
||||
days_reg[3:0] <= 0;
|
||||
days_reg[5:4] <= days_reg[5:4] + 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
// DM binary data mode
|
||||
if (seconds_reg != 8'h3B) seconds_reg <= seconds_reg + 1'd1;
|
||||
else begin
|
||||
seconds_reg <= 0;
|
||||
if (minutes_reg != 8'h3B) minutes_reg <= minutes_reg + 1'd1;
|
||||
else begin
|
||||
minutes_reg <= 0;
|
||||
if ({b_reg[1], hours_reg[7], hours_reg[3:0]} == 6'b001100) hours_reg[7:0] <= 8'b10000001;
|
||||
else if (({b_reg[1], hours_reg[7], hours_reg[3:0]} != 6'b011100) & ({b_reg[1], hours_reg[4:0]} != 6'b110111)) hours_reg[4:0] <= hours_reg[4:0] + 1'd1;
|
||||
else begin
|
||||
if (b_reg[1] == 1'b0) hours_reg[7:0] <= 1;
|
||||
else hours_reg <= 0;
|
||||
|
||||
if (weeks_reg != 7) weeks_reg <= weeks_reg + 1'd1;
|
||||
else weeks_reg <= 1; // Sunday = 1
|
||||
|
||||
if (({month_reg, days_reg, leap_reg} == {16'h021C, 2'b01}) | ({month_reg, days_reg, leap_reg} == {16'h021C, 2'b10}) | ({month_reg, days_reg, leap_reg} == {16'h021C, 2'b11}) | ({month_reg, days_reg, leap_reg} == {16'h021D, 2'b00}) | ({month_reg, days_reg} == 16'h041E) | ({month_reg, days_reg} == 16'h061E) | ({month_reg, days_reg} == 16'h091E) | ({month_reg, days_reg} == 16'h0B1E) | (days_reg == 8'h1F)) begin
|
||||
days_reg <= 1;
|
||||
if (month_reg != 8'h0C) month_reg <= month_reg + 1'd1;
|
||||
else begin
|
||||
month_reg <= 1;
|
||||
leap_reg[1:0] <= leap_reg[1:0] + 1'd1;
|
||||
if (year_reg != 8'h63) year_reg <= year_reg + 1'd1;
|
||||
else year_reg <= 0;
|
||||
end
|
||||
end else days_reg <= days_reg + 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 50 Bytes of General Purpose RAM
|
||||
dpram #(.DATAWIDTH(8), .ADDRWIDTH(8), .MEM_INIT_FILE("rtl/periph/CMOS.mif")) CMOS
|
||||
(
|
||||
.clock (CLK),
|
||||
.address_a (A),
|
||||
.data_a (DI),
|
||||
.wren_a (WR & CS),
|
||||
.q_a (CMOS_Dout)
|
||||
);
|
||||
|
||||
endmodule
|
||||
60
rtl/periph/vdac.v
Normal file
60
rtl/periph/vdac.v
Normal file
@ -0,0 +1,60 @@
|
||||
module vdac
|
||||
(
|
||||
input wire mode,
|
||||
|
||||
input wire [4:0] o_r, // input from FPGA
|
||||
input wire [4:0] o_g,
|
||||
input wire [4:0] o_b,
|
||||
|
||||
output wire [7:0] v_r, // output to VDAC
|
||||
output wire [7:0] v_g,
|
||||
output wire [7:0] v_b
|
||||
);
|
||||
|
||||
vdac_lut vdac_lut_r (.mode(mode), .in(o_r), .out(v_r));
|
||||
vdac_lut vdac_lut_g (.mode(mode), .in(o_g), .out(v_g));
|
||||
vdac_lut vdac_lut_b (.mode(mode), .in(o_b), .out(v_b));
|
||||
|
||||
endmodule
|
||||
|
||||
module vdac_lut
|
||||
(
|
||||
input wire mode,
|
||||
input wire [4:0] in,
|
||||
output wire [7:0] out
|
||||
);
|
||||
|
||||
reg [7:0] lut;
|
||||
assign out = mode ? {in, 3'b0} : lut;
|
||||
|
||||
always @*
|
||||
case (in)
|
||||
5'd0: lut = 8'd0;
|
||||
5'd1: lut = 8'd10;
|
||||
5'd2: lut = 8'd21;
|
||||
5'd3: lut = 8'd31;
|
||||
5'd4: lut = 8'd42;
|
||||
5'd5: lut = 8'd53;
|
||||
5'd6: lut = 8'd63;
|
||||
5'd7: lut = 8'd74;
|
||||
5'd8: lut = 8'd85;
|
||||
5'd9: lut = 8'd95;
|
||||
5'd10: lut = 8'd106;
|
||||
5'd11: lut = 8'd117;
|
||||
5'd12: lut = 8'd127;
|
||||
5'd13: lut = 8'd138;
|
||||
5'd14: lut = 8'd149;
|
||||
5'd15: lut = 8'd159;
|
||||
5'd16: lut = 8'd170;
|
||||
5'd17: lut = 8'd181;
|
||||
5'd18: lut = 8'd191;
|
||||
5'd19: lut = 8'd202;
|
||||
5'd20: lut = 8'd213;
|
||||
5'd21: lut = 8'd223;
|
||||
5'd22: lut = 8'd234;
|
||||
5'd23: lut = 8'd245;
|
||||
5'd24: lut = 8'd255;
|
||||
default: lut = 8'd255;
|
||||
endcase
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user