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update tsconf to commit 83afbba6f5d366f96297028aa3d64512fa254a51
This commit is contained in:
Eugene Lozovoy
267
rtl/dram/arbiter.v
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267
rtl/dram/arbiter.v
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@ -0,0 +1,267 @@
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`include "tune.v"
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// PentEvo project (c) NedoPC 2008-2011
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//
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// DRAM arbiter. Shares DRAM between CPU, video data fetcher and other devices
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//
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// Arbitration is made on full 8-cycle access blocks. Each cycle is defined by dram.v and consists of 4 fpga clocks.
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// During each access block, there can be either no videodata access, 1 videodata access, 2, 4 or 8 accesses.
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// All spare cycles can be used by CPU or other devices. If no device uses memory in the given cycle, refresh cycle is performed.
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//
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// In each access block, videodata accesses are spreaded all over the block so that CPU receives cycle
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// as fast as possible, until there is absolute need to fetch remaining video data.
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//
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// Examples:
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//
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// | access block | 4 video accesses during block, no processor accesses. video accesses are done
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// | vid | vid | vid | vid | ref | ref | ref | ref | as soon as possible, spare cycles are refresh ones
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//
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// | access block | 4 video accesses during block, processor requests access every other cycle
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// | vid | prc | vid | prc | vid | prc | vid | prc |
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//
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// | access block | 4 video accesses, processor begins requesting cycles continously from second one
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// | vid | prc | prc | prc | prc | vid | vid | vid | so it is given cycles while there is such possibility. after that processor
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// can't access mem until the end of access block and stalls
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//
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// | access block | 8 video accesses, processor stalls, if it is requesting cycles
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// | vid | vid | vid | vid | vid | vid | vid | vid |
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//
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// | access block | 2 video accesses, single processor request, other cycles are refresh ones
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// | vid | vid | ref | ref | cpu | ref | ref | ref |
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//
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// | access block | 4 video accesses, single processor request, other cycles are refresh ones
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// | vid | vid | cpu | vid | vid | ref | ref | ref |
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//
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// access block begins at any dram cycle, then blocks video_go back-to-back
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//
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// key signals are video_go and XXX_req, sampled at the end of each dram cycle. Must be set to the module at c3 clock cycle.
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// CPU can have either normal or lower access priority to the DRAM.
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// At the INT active (32 of 3.5MHz clocks) the priority is raised to normal, so that CPU won't miss its interrupt.
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// This should be considered if dummy RAM access used for waiting for the end of DMA operation instead of status bit polling.
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//
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// DRAM access priority:
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// Z80 normal Z80 low
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// - VIDEO - VIDEO
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// - CPU - TS
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// - TM - TM
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// - TS - DMA
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// - DMA - CPU
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module arbiter
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(
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input wire clk,
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input wire c1,
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input wire c2,
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input wire c3,
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input wire cyc,
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// dram.v interface
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output wire [21:0] dram_addr, // address for dram access
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output wire dram_req, // dram request
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output wire dram_rnw, // Read-NotWrite
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output wire [ 1:0] dram_bsel, // byte select: bsel[1] for wrdata[15:8], bsel[0] for wrdata[7:0]
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output wire [15:0] dram_wrdata, // data to be written
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// video
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input wire [20:0] video_addr, // during access block, only when video_strobe==1
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input wire video_go, // start video access blocks
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input wire [ 4:0] video_bw, // [4:3] - total cycles: 11 = 8 / 01 = 4 / 00 = 2
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// [2:0] - need cycles
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output wire video_pre_next, // (c1)
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output wire video_next, // (c2) at this signal video_addr may be changed; it is one clock leading the video_strobe
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output wire video_strobe, // (c3) one-cycle strobe meaning that video_data is available
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output wire next_vid, // used for TM prefetch
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// CPU
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input wire [20:0] cpu_addr,
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input wire [ 7:0] cpu_wrdata,
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input wire cpu_req,
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input wire cpu_rnw,
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input wire cpu_wrbsel,
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input wire cpu_csrom,
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output reg cpu_next, // next cycle is allowed to be used by CPU
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output reg cpu_strobe,
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output reg cpu_latch,
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output wire curr_cpu_o,
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// DMA
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input wire [20:0] dma_addr,
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input wire [15:0] dma_wrdata,
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input wire dma_req,
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input wire dma_rnw,
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output wire dma_next,
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// TS
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input wire [20:0] ts_addr,
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input wire ts_req,
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output wire ts_pre_next,
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output wire ts_next,
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// TM
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input wire [20:0] tm_addr,
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input wire tm_req,
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output wire tm_next,
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// ROM loader
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input wire loader_clk,
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input wire [15:0] loader_addr,
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input wire [7:0] loader_data,
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input wire loader_wr
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);
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localparam CYCLES = 6;
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localparam CYC_CPU = 6'b000001;
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localparam CYC_VID = 6'b000010;
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localparam CYC_TS = 6'b000100;
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localparam CYC_TM = 6'b001000;
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localparam CYC_DMA = 6'b010000;
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localparam CYC_LOADER = 6'b100000;
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localparam CYC_FREE = 6'b000000;
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localparam CPU = 0;
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localparam VIDEO = 1;
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localparam TS = 2;
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localparam TM = 3;
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localparam DMA = 4;
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localparam LOADER = 5;
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reg [CYCLES-1:0] curr_cycle; // type of the cycle in progress
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reg [CYCLES-1:0] next_cycle; // type of the next cycle
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reg [2:0] blk_rem = 0; // remaining accesses in a block (7..0)
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reg [2:0] vid_rem = 0; // remaining video accesses in block
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reg stall = 0;
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wire dev_over_cpu = 0; // can be used to rise devices priority over CPU
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wire next_cpu = next_cycle[CPU];
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assign next_vid = next_cycle[VIDEO];
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wire next_ts = next_cycle[TS];
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wire next_tm = next_cycle[TM];
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wire next_dma = next_cycle[DMA];
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wire next_loader = next_cycle[LOADER];
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wire curr_cpu = curr_cycle[CPU];
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wire curr_vid = curr_cycle[VIDEO];
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wire curr_ts = curr_cycle[TS];
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wire curr_tm = curr_cycle[TM];
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wire curr_dma = curr_cycle[DMA];
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wire curr_loader = curr_cycle[LOADER];
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assign curr_cpu_o = curr_cpu;
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// track blk_rem counter:
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// how many cycles left to the end of block (7..0)
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wire video_start = ~|blk_rem;
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wire [2:0] blk_nrem = (video_start && video_go) ? {video_bw[4:3], 1'b1} : (video_start ? 3'd0 : (blk_rem - 3'd1));
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wire bw_full = ~|{video_bw[4] & video_bw[2], video_bw[3] & video_bw[1], video_bw[0]}; // stall when 000/00/0
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wire video_only = stall || (vid_rem == blk_rem);
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wire video_idle = ~|vid_rem;
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always @(posedge clk) if (c3)
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begin
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blk_rem <= blk_nrem;
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if (video_start)
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stall <= bw_full & video_go;
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end
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// track vid_rem counter
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// how many video cycles left to the end of block (7..0)
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wire [2:0] vidmax = {video_bw[2:0]}; // number of cycles for video access
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wire [2:0] vid_nrem_next = video_idle ? 3'd0 : (vid_rem - 3'd1);
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wire [2:0] vid_nrem_start = (cpu_req && !dev_over_cpu) ? vidmax : (vidmax - 3'd1);
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wire [2:0] vid_nrem = (video_go && video_start) ? vid_nrem_start : (next_vid ? vid_nrem_next : vid_rem);
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always @(posedge clk) if (c3)
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vid_rem <= vid_nrem;
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reg loader_wr0;
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reg [7:0] loader_data0;
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always @(posedge loader_clk) begin
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if (loader_wr) begin
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loader_wr0 <= 1'd1;
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loader_data0 <= loader_data;
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end
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else if (cyc) begin
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loader_wr0 <= 1'd0;
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end
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end
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// next cycle decision
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wire [CYCLES-1:0] cyc_dev = tm_req ? CYC_TM : (ts_req ? CYC_TS : CYC_DMA);
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wire dev_req = ts_req || tm_req || dma_req;
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always @*
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if (loader_wr0) begin
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cpu_next = 1'b0;
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next_cycle = CYC_LOADER;
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end
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else
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if (video_start) // video burst start
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if (video_go) // video active
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begin
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cpu_next = dev_over_cpu ? 1'b0 : !bw_full;
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next_cycle = dev_over_cpu ? CYC_VID : (bw_full ? CYC_VID : (cpu_req ? CYC_CPU : CYC_VID));
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end
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else // video idle
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begin
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cpu_next = !dev_over_cpu;
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next_cycle = dev_over_cpu ? cyc_dev : (cpu_req ? CYC_CPU : (dev_req ? cyc_dev : CYC_FREE));
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end
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else // video burst in progress
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begin
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cpu_next = dev_over_cpu ? 1'b0 : !video_only;
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next_cycle = video_only ? CYC_VID : (dev_over_cpu ? cyc_dev : (cpu_req ? CYC_CPU : (!video_idle ? CYC_VID : (dev_req ? cyc_dev : CYC_FREE))));
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end
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always @(posedge clk) if (c3)
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curr_cycle <= next_cycle;
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// DRAM interface
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assign dram_wrdata = curr_loader? {2{loader_data0}} : curr_dma ? dma_wrdata : {2{cpu_wrdata[7:0]}}; // write data has to be clocked at c0 in dram.v
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assign dram_bsel[1:0] = next_loader? {loader_addr[0], ~loader_addr[0]} : next_dma ? 2'b11 : {cpu_wrbsel, ~cpu_wrbsel};
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assign dram_req = |next_cycle;
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assign dram_rnw = next_loader? 1'b0 : next_cpu ? cpu_rnw : (next_dma ? dma_rnw : 1'b1);
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assign dram_addr = {22{next_loader}} & { 1'b1, 6'b000000, loader_addr[15:1] }
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| {22{next_cpu}} & { cpu_csrom, {6{~cpu_csrom}} & cpu_addr[20:15], cpu_addr[14:0] }
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| {22{next_vid}} & { 1'b0, video_addr }
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| {22{next_ts}} & { 1'b0, ts_addr }
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| {22{next_tm}} & { 1'b0, tm_addr }
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| {22{next_dma}} & { 1'b0, dma_addr };
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reg cpu_rnw_r;
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always @(posedge clk) if (c3)
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cpu_rnw_r <= cpu_rnw;
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// read strobes generation for video and cpu
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always @(posedge clk)
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if (c1)
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begin
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cpu_strobe <= curr_cpu && cpu_rnw_r;
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cpu_latch <= curr_cpu && cpu_rnw_r;
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end
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else if (c2)
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cpu_strobe <= 1'b0;
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else if (c3)
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cpu_latch <= 1'b0;
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assign video_pre_next = curr_vid & c1;
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assign video_next = curr_vid & c2;
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assign video_strobe = curr_vid && c3;
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assign ts_pre_next = curr_ts & c1;
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assign ts_next = curr_ts & c2;
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assign tm_next = curr_tm & c2;
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assign dma_next = curr_dma & c2;
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endmodule
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72
rtl/dram/dpram.v
Normal file
72
rtl/dram/dpram.v
Normal file
@ -0,0 +1,72 @@
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module dpram #(parameter DATAWIDTH=8, ADDRWIDTH=8, NUMWORDS=1<<ADDRWIDTH, MEM_INIT_FILE="")
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(
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input clock,
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input [ADDRWIDTH-1:0] address_a,
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input [DATAWIDTH-1:0] data_a,
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input wren_a,
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output [DATAWIDTH-1:0] q_a,
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input [ADDRWIDTH-1:0] address_b,
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input [DATAWIDTH-1:0] data_b,
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input wren_b,
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output [DATAWIDTH-1:0] q_b
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);
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altsyncram altsyncram_component (
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.address_a (address_a),
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.address_b (address_b),
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.clock0 (clock),
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.data_a (data_a),
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.data_b (data_b),
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.wren_a (wren_a),
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.wren_b (wren_b),
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.q_a (q_a),
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.q_b (q_b),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.eccstatus (),
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.rden_a (1'b1),
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.rden_b (1'b1));
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defparam
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altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
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altsyncram_component.address_reg_b = "CLOCK0",
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altsyncram_component.indata_reg_b = "CLOCK0",
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altsyncram_component.numwords_a = NUMWORDS,
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altsyncram_component.numwords_b = NUMWORDS,
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altsyncram_component.widthad_a = ADDRWIDTH,
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altsyncram_component.widthad_b = ADDRWIDTH,
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altsyncram_component.width_a = DATAWIDTH,
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altsyncram_component.width_b = DATAWIDTH,
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altsyncram_component.width_byteena_a = 1,
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altsyncram_component.width_byteena_b = 1,
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altsyncram_component.init_file = MEM_INIT_FILE,
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.intended_device_family = "Cyclone III",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_a = "UNREGISTERED",
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altsyncram_component.outdata_reg_b = "UNREGISTERED",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
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altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
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altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ";
|
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endmodule
|
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168
rtl/dram/sdram.v
Normal file
168
rtl/dram/sdram.v
Normal file
@ -0,0 +1,168 @@
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// READ 25 26 27 21 22 23 24
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||||
// RAS CAS read
|
||||
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
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||||
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
|
||||
// T0 T1 T2 T3 T4 T5 T6
|
||||
// 5.95ns ACT READ DQDQDQDQD
|
||||
// tAC=6 tOH=3
|
||||
//
|
||||
// WRITE 25 26 27 22 23 24
|
||||
// RAS CASWEDQ
|
||||
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
|
||||
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
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||||
// T0 T1 T2 T3 T4 T5
|
||||
// 5.95ns ACT WRITE
|
||||
//
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||||
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||||
module sdram
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||||
(
|
||||
// Memory port
|
||||
input clk,
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||||
input cyc,
|
||||
|
||||
input curr_cpu,
|
||||
input [1:0] bsel, // Active HI
|
||||
input [23:0] A,
|
||||
input [15:0] DI,
|
||||
output reg [15:0] DO,
|
||||
output reg [15:0] DO_cpu,
|
||||
input REQ,
|
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input RNW,
|
||||
|
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// SDRAM Pin
|
||||
inout reg [15:0] SDRAM_DQ,
|
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output reg [12:0] SDRAM_A,
|
||||
output reg [1:0] SDRAM_BA,
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output SDRAM_DQML,
|
||||
output SDRAM_DQMH,
|
||||
output SDRAM_nCS,
|
||||
output SDRAM_nCAS,
|
||||
output SDRAM_nRAS,
|
||||
output SDRAM_nWE,
|
||||
output SDRAM_CKE,
|
||||
output SDRAM_CLK
|
||||
);
|
||||
|
||||
reg [2:0] sdr_cmd;
|
||||
|
||||
localparam SdrCmd_xx = 3'b111; // no operation
|
||||
localparam SdrCmd_ac = 3'b011; // activate
|
||||
localparam SdrCmd_rd = 3'b101; // read
|
||||
localparam SdrCmd_wr = 3'b100; // write
|
||||
localparam SdrCmd_pr = 3'b010; // precharge all
|
||||
localparam SdrCmd_re = 3'b001; // refresh
|
||||
localparam SdrCmd_ms = 3'b000; // mode regiser set
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [4:0] state;
|
||||
reg rd;
|
||||
reg [8:0] col;
|
||||
reg [1:0] dqm;
|
||||
reg [15:0] data;
|
||||
reg [23:0] Ar;
|
||||
reg rq;
|
||||
|
||||
sdr_cmd <= SdrCmd_xx;
|
||||
data <= SDRAM_DQ;
|
||||
SDRAM_DQ <= 16'bZ;
|
||||
state <= state + 1'd1;
|
||||
|
||||
case (state)
|
||||
|
||||
// Init
|
||||
0: begin
|
||||
sdr_cmd <= SdrCmd_pr; // PRECHARGE
|
||||
SDRAM_A <= 0;
|
||||
SDRAM_BA <= 0;
|
||||
end
|
||||
|
||||
// REFRESH
|
||||
3,10: begin
|
||||
sdr_cmd <= SdrCmd_re;
|
||||
end
|
||||
|
||||
// LOAD MODE REGISTER
|
||||
17: begin
|
||||
sdr_cmd <= SdrCmd_ms;
|
||||
SDRAM_A <= {3'b000, 1'b1, 2'b00, 3'b010, 1'b0, 3'b000};
|
||||
end
|
||||
|
||||
// Idle
|
||||
24: begin
|
||||
if (rd) begin
|
||||
DO <= data;
|
||||
if (curr_cpu) DO_cpu <= data;
|
||||
end
|
||||
|
||||
state <= state;
|
||||
Ar <= A;
|
||||
dqm <= RNW ? 2'b00 : ~bsel;
|
||||
rd <= 0;
|
||||
|
||||
if(cyc) begin
|
||||
rq <= REQ;
|
||||
rd <= REQ & RNW;
|
||||
state <= state + 1'd1;
|
||||
end
|
||||
end
|
||||
|
||||
// Start
|
||||
25: begin
|
||||
if (rq) begin
|
||||
{SDRAM_A,SDRAM_BA,col} <= Ar;
|
||||
sdr_cmd <= SdrCmd_ac;
|
||||
end else begin
|
||||
sdr_cmd <= SdrCmd_re;
|
||||
state <= 19;
|
||||
end
|
||||
end
|
||||
|
||||
// Single read/write - with auto precharge
|
||||
27: begin
|
||||
SDRAM_A <= {dqm, 2'b10, col};
|
||||
state <= 21;
|
||||
if (rd) sdr_cmd <= SdrCmd_rd;
|
||||
else begin
|
||||
sdr_cmd <= SdrCmd_wr;
|
||||
SDRAM_DQ <= DI;
|
||||
state <= 22;
|
||||
end
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
assign SDRAM_CKE = 1;
|
||||
assign SDRAM_nCS = 0;
|
||||
assign SDRAM_nRAS = sdr_cmd[2];
|
||||
assign SDRAM_nCAS = sdr_cmd[1];
|
||||
assign SDRAM_nWE = sdr_cmd[0];
|
||||
assign SDRAM_DQML = SDRAM_A[11];
|
||||
assign SDRAM_DQMH = SDRAM_A[12];
|
||||
|
||||
altddio_out
|
||||
#(
|
||||
.extend_oe_disable("OFF"),
|
||||
.intended_device_family("Cyclone III"),
|
||||
.invert_output("OFF"),
|
||||
.lpm_hint("UNUSED"),
|
||||
.lpm_type("altddio_out"),
|
||||
.oe_reg("UNREGISTERED"),
|
||||
.power_up_high("OFF"),
|
||||
.width(1)
|
||||
)
|
||||
sdramclk_ddr
|
||||
(
|
||||
.datain_h(1'b0),
|
||||
.datain_l(1'b1),
|
||||
.outclock(clk),
|
||||
.dataout(SDRAM_CLK),
|
||||
.aclr(1'b0),
|
||||
.aset(1'b0),
|
||||
.oe(1'b1),
|
||||
.outclocken(1'b1),
|
||||
.sclr(1'b0),
|
||||
.sset(1'b0)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user