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https://github.com/UzixLS/TSConf_MiST.git
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update tsconf to commit 83afbba6f5d366f96297028aa3d64512fa254a51
This commit is contained in:
Eugene Lozovoy
429
rtl/common/dma.v
Normal file
429
rtl/common/dma.v
Normal file
@ -0,0 +1,429 @@
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// This module serves direct DRAM-to-device data transfer
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`include "tune.v"
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module dma
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(
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// clocks
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input wire clk,
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input wire c2,
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input wire rst_n,
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// interface
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`ifdef FDR
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input wire [9:0] dmaport_wr,
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`else
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input wire [8:0] dmaport_wr,
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`endif
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output wire dma_act,
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output reg [15:0] data = 0,
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output wire [ 7:0] wraddr,
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output wire int_start,
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// Z80
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input wire [7:0] zdata,
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// DRAM interface
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output wire [20:0] dram_addr,
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input wire [15:0] dram_rddata,
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output wire [15:0] dram_wrdata,
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output wire dram_req,
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output wire dram_rnw,
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input wire dram_next,
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// SPI interface
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input wire [7:0] spi_rddata,
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output wire [7:0] spi_wrdata,
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output wire spi_req,
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input wire spi_stb,
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// WTPORT interface
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input wire [7:0] wtp_rddata,
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// output wire [7:0] wtp_wrdata,
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output wire wtp_req,
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input wire wtp_stb,
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// IDE interface
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input wire [15:0] ide_in,
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output wire [15:0] ide_out,
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output wire ide_req,
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output wire ide_rnw,
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input wire ide_stb,
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`ifdef FDR
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// FDD interface
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input wire [7:0] fdr_in,
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output wire fdr_req,
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input wire fdr_stb,
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input wire fdr_stop,
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`endif
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// CRAM interface
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output wire cram_we,
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// SFILE interface
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output wire sfile_we
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);
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// mode:
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// 0 - device to RAM (read from device)
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// 1 - RAM to device (write to device)
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wire dma_saddrl = dmaport_wr[0];
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wire dma_saddrh = dmaport_wr[1];
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wire dma_saddrx = dmaport_wr[2];
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wire dma_daddrl = dmaport_wr[3];
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wire dma_daddrh = dmaport_wr[4];
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wire dma_daddrx = dmaport_wr[5];
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wire dma_len = dmaport_wr[6];
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wire dma_launch = dmaport_wr[7];
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wire dma_num = dmaport_wr[8];
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`ifdef FDR
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wire dma_numh = dmaport_wr[9];
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`endif
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// devices
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localparam DEV_RAM = 3'b001;
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localparam DEV_BLT1 = 4'b1001;
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`ifdef XTR_FEAT
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localparam DEV_BLT2 = 4'b0110;
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`endif
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localparam DEV_FIL = 4'b0100;
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localparam DEV_SPI = 3'b010;
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localparam DEV_IDE = 3'b011;
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localparam DEV_CRM = 4'b1100;
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localparam DEV_SFL = 4'b1101;
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localparam DEV_FDD = 4'b0101;
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localparam DEV_WTP = 4'b0111;
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wire state_dev;
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wire ide_int_stb;
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wire byte_sw_stb;
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wire spi_int_stb;
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wire wtp_int_stb;
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reg dma_salgn;
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reg dma_dalgn;
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reg dma_asz;
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reg phase; // 0 - read / 1 - write
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reg phase_blt; // 0 - source / 1 - destination
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reg bsel; // 0 - lsb / 1 - msb
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reg dma_opt;
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reg [3:0] device;
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wire [2:0] dev_bid = device[2:0]; // bidirectional
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wire [3:0] dev_uni = device[3:0]; // unidirectional
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wire dma_wnr = device[3]; // 0 - device to RAM / 1 - RAM to device
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`ifdef XTR_FEAT
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wire dv_ram = (dev_uni == DEV_RAM) || (dev_uni == DEV_BLT1) || (dev_uni == DEV_BLT2) || (dev_uni == DEV_FIL);
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wire dv_blt = (dev_uni == DEV_BLT1) || (dev_uni == DEV_BLT2);
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`else
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wire dv_ram = (dev_uni == DEV_RAM) || (dev_uni == DEV_BLT1) || (dev_uni == DEV_FIL);
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wire dv_blt = (dev_uni == DEV_BLT1);
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`endif
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wire dv_fil = (dev_uni == DEV_FIL);
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wire dv_spi = (dev_bid == DEV_SPI);
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wire dv_ide = (dev_bid == DEV_IDE);
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wire dv_crm = (dev_uni == DEV_CRM);
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wire dv_sfl = (dev_uni == DEV_SFL);
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wire dv_wtp = (dev_uni == DEV_WTP);
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`ifdef FDR
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wire dv_fdd = (dev_uni == DEV_FDD);
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`endif
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wire dev_req = dma_act && state_dev;
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wire dev_stb = cram_we || sfile_we || ide_int_stb || (byte_sw_stb && bsel && dma_act);
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`ifdef FDR
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assign byte_sw_stb = spi_int_stb || wtp_int_stb || fdr_int_stb;
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`else
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assign byte_sw_stb = spi_int_stb || wtp_int_stb;
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`endif
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// blitter
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// Mode 1
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wire [7:0] blt1_data10 = |data[7:0] ? data[7:0] : dram_rddata[7:0];
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wire [7:0] blt1_data32 = |data[15:8] ? data[15:8] : dram_rddata[15:8];
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wire [3:0] blt1_data0 = |data[3:0] ? data[3:0] : dram_rddata[3:0];
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wire [3:0] blt1_data1 = |data[7:4] ? data[7:4] : dram_rddata[7:4];
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wire [3:0] blt1_data2 = |data[11:8] ? data[11:8] : dram_rddata[11:8];
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wire [3:0] blt1_data3 = |data[15:12] ? data[15:12] : dram_rddata[15:12];
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wire [7:0] blt1_data_l = dma_asz ? blt1_data10 : {blt1_data1, blt1_data0};
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wire [7:0] blt1_data_h = dma_asz ? blt1_data32 : {blt1_data3, blt1_data2};
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wire [15:0] blt1_rddata = {blt1_data_h, blt1_data_l};
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`ifdef XTR_FEAT
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// Mode 2
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localparam msk = 8'd255;
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wire [8:0] sum80 = data[7:0] + dram_rddata[7:0];
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wire [8:0] sum81 = data[15:8] + dram_rddata[15:8];
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wire [4:0] sum40 = data[3:0] + dram_rddata[3:0];
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wire [4:0] sum41 = data[7:4] + dram_rddata[7:4];
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wire [4:0] sum42 = data[11:8] + dram_rddata[11:8];
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wire [4:0] sum43 = data[15:12] + dram_rddata[15:12];
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wire [7:0] blt2_8_data0 = ((sum80 > msk) && dma_opt) ? msk : sum80[7:0];
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wire [7:0] blt2_8_data1 = ((sum81 > msk) && dma_opt) ? msk : sum81[7:0];
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wire [3:0] blt2_4_data0 = ((sum40 > msk[3:0]) && dma_opt) ? msk[3:0] : sum40[3:0];
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wire [3:0] blt2_4_data1 = ((sum41 > msk[3:0]) && dma_opt) ? msk[3:0] : sum41[3:0];
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wire [3:0] blt2_4_data2 = ((sum42 > msk[3:0]) && dma_opt) ? msk[3:0] : sum42[3:0];
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wire [3:0] blt2_4_data3 = ((sum43 > msk[3:0]) && dma_opt) ? msk[3:0] : sum43[3:0];
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wire [7:0] blt2_data_0 = dma_asz ? blt2_8_data0 : {blt2_4_data1, blt2_4_data0};
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wire [7:0] blt2_data_1 = dma_asz ? blt2_8_data1 : {blt2_4_data3, blt2_4_data2};
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wire [15:0] blt2_rddata = {blt2_data_1, blt2_data_0};
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wire [15:0] blt_rddata = (dev_uni == DEV_BLT1) ? blt1_rddata : blt2_rddata;
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`else // XTR_FEAT
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wire [15:0] blt_rddata = blt1_rddata;
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`endif
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// states
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wire state_rd = ~phase;
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wire state_wr = phase;
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assign state_dev = !dv_ram && (dma_wnr ^ !phase);
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wire state_mem = dv_ram || (dma_wnr ^ phase);
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// states processing
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wire blt_hook = dv_blt && !phase_blt && !phase;
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wire phase_end_ram = state_mem && dram_next && !blt_hook;
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wire phase_end_dev = state_dev && dev_stb;
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wire phase_end = phase_end_ram || phase_end_dev;
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wire fil_hook = dv_fil && phase;
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wire phase_blt_end = state_mem && dram_next && !phase;
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// blitter cycles:
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// phase phase_blt blt_hook activity
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// 0 0 1 read src
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// 0 1 0 read dst
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// 1 1 0 write dst
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always @(posedge clk)
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if (dma_launch) // write to DMACtrl - launch of DMA burst
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begin
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dma_opt <= zdata[6];
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dma_salgn <= zdata[5];
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dma_dalgn <= zdata[4];
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dma_asz <= zdata[3];
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device <= {zdata[7], zdata[2:0]};
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phase <= 1'b0;
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phase_blt <= 1'b0;
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bsel <= 1'b0;
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end
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else
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begin
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if (phase_end && !fil_hook)
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phase <= ~phase;
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if (phase_blt_end)
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phase_blt <= ~phase_blt;
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if (byte_sw_stb)
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bsel <= ~bsel;
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end
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// data aquiring
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always @(posedge clk)
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if (state_rd)
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begin
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if (dram_next)
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data <= (dv_blt && phase_blt) ? blt_rddata : dram_rddata;
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if (ide_int_stb)
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data <= ide_in;
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if (spi_int_stb)
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begin
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if (bsel)
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data[15:8] <= spi_rddata;
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else
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data[7:0] <= spi_rddata;
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end
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if (wtp_int_stb)
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begin
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if (bsel)
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data[15:8] <= wtp_rddata;
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else
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data[7:0] <= wtp_rddata;
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end
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`ifdef FDR
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if (fdr_int_stb)
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begin
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if (bsel)
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data[15:8] <= fdr_in;
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else
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data[7:0] <= fdr_in;
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end
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`endif
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end
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// counter processing
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reg [7:0] b_len; // length of burst
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reg [7:0] b_ctr; // counter for cycles in burst
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wire [8:0] b_ctr_dec = {1'b0, b_ctr[7:0]} - 9'b1;
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wire next_burst = b_ctr_dec[8];
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wire [7:0] b_ctr_next = next_burst ? b_len : b_ctr_dec[7:0];
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`ifdef FDR
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reg [9:0] b_num; // number of bursts
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reg [10:0] n_ctr; // counter for bursts
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wire [10:0] n_ctr_dec = n_ctr - next_burst;
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assign dma_act = !n_ctr[10];
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`else
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reg [7:0] b_num; // number of bursts
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reg [8:0] n_ctr; // counter for bursts
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wire [8:0] n_ctr_dec = n_ctr - next_burst;
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assign dma_act = !n_ctr[8];
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`endif
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always @(posedge clk)
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`ifdef FDR
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if (!rst_n || (dv_fdd && fdr_stop))
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n_ctr[10] <= 1'b1;
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`else
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if (!rst_n)
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n_ctr[8] <= 1'b1;
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`endif
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else if (dma_launch)
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begin
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b_ctr <= b_len;
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n_ctr <= {1'b0, b_num};
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end
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else if (phase && phase_end) // cycle processed
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begin
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b_ctr <= b_ctr_next;
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n_ctr <= n_ctr_dec;
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end
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// loading of burst parameters
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always @(posedge clk)
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begin
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if (dma_len)
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b_len <= zdata;
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if (dma_num)
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`ifdef FDR
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b_num[7:0] <= zdata;
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if (dma_numh)
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b_num[9:8] <= zdata[1:0];
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`else
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b_num <= zdata;
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`endif
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end
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// address processing
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// source
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reg [20:0] s_addr; // current source address
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reg [7:0] s_addr_r; // source lower address
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wire [8:0] s_addr_inc_l = {1'b0, s_addr[7:0]} + 9'b1;
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wire [1:0] s_addr_add_h = dma_salgn ? {next_burst && dma_asz, next_burst && !dma_asz} : {s_addr_inc_l[8], 1'b0};
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wire [13:0] s_addr_next_h = s_addr[20:7] + s_addr_add_h;
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wire [7:0] s_addr_next_l = (dma_salgn && next_burst) ? s_addr_r : s_addr_inc_l[7:0];
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wire s_addr_next_m = dma_salgn ? (dma_asz ? s_addr_next_l[7] : s_addr_next_h[0]) : s_addr_inc_l[7];
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wire [20:0] s_addr_next = {s_addr_next_h[13:1], s_addr_next_m, s_addr_next_l[6:0]};
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always @(posedge clk)
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if ((dram_next || dev_stb) && state_rd && (!dv_blt || !phase_blt)) // increment RAM source addr
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s_addr <= s_addr_next;
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else
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begin
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if (dma_saddrl)
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begin
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s_addr[6:0] <= zdata[7:1];
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s_addr_r[6:0] <= zdata[7:1];
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end
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if (dma_saddrh)
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begin
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s_addr[12:7] <= zdata[5:0];
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s_addr_r[7] <= zdata[0];
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end
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if (dma_saddrx)
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s_addr[20:13] <= zdata;
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end
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// destination
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reg [20:0] d_addr; // current dest address
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reg [7:0] d_addr_r; // dest lower address
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wire [8:0] d_addr_inc_l = {1'b0, d_addr[7:0]} + 9'b1;
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wire [1:0] d_addr_add_h = dma_dalgn ? {next_burst && dma_asz, next_burst && !dma_asz} : {d_addr_inc_l[8], 1'b0};
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wire [13:0] d_addr_next_h = d_addr[20:7] + d_addr_add_h;
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wire [7:0] d_addr_next_l = (dma_dalgn && next_burst) ? d_addr_r : d_addr_inc_l[7:0];
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wire d_addr_next_m = dma_dalgn ? (dma_asz ? d_addr_next_l[7] : d_addr_next_h[0]) : d_addr_inc_l[7];
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wire [20:0] d_addr_next = {d_addr_next_h[13:1], d_addr_next_m, d_addr_next_l[6:0]};
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always @(posedge clk)
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if ((dram_next || dev_stb) && state_wr) // increment RAM dest addr
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d_addr <= d_addr_next;
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else
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begin
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if (dma_daddrl)
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begin
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d_addr[6:0] <= zdata[7:1];
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d_addr_r[6:0] <= zdata[7:1];
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end
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if (dma_daddrh)
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begin
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d_addr[12:7] <= zdata[5:0];
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d_addr_r[7] <= zdata[0];
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end
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if (dma_daddrx)
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d_addr[20:13] <= zdata;
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end
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// INT generation
|
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reg dma_act_r = 0;
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always @(posedge clk)
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dma_act_r <= dma_act && rst_n;
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assign int_start = !dma_act && dma_act_r;
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assign wraddr = d_addr[7:0];
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// DRAM
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assign dram_addr = state_rd ? ((!dv_blt || !phase_blt) ? s_addr : d_addr) : d_addr;
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assign dram_wrdata = data;
|
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assign dram_req = dma_act && state_mem;
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assign dram_rnw = state_rd;
|
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|
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assign cram_we = dev_req && dv_crm && state_wr;
|
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assign sfile_we = dev_req && dv_sfl && state_wr;
|
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|
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`ifdef FDR
|
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// FDD
|
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wire fdr_int_stb = dv_fdd && fdr_stb;
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assign fdr_req = dev_req && dv_fdd;
|
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`endif
|
||||
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// SPI
|
||||
assign spi_int_stb = dv_spi && spi_stb;
|
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assign spi_wrdata = {8{state_rd}} | (bsel ? data[15:8] : data[7:0]); // send FF on read cycles
|
||||
assign spi_req = dev_req && dv_spi;
|
||||
|
||||
// WTPORT
|
||||
assign wtp_int_stb = dv_wtp && wtp_stb;
|
||||
assign wtp_req = dev_req && dv_wtp;
|
||||
|
||||
// IDE
|
||||
assign ide_int_stb = dv_ide && ide_stb;
|
||||
assign ide_out = data;
|
||||
assign ide_req = dev_req && dv_ide;
|
||||
assign ide_rnw = state_rd;
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user