mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 23:01:37 +03:00
update tsconf to commit 83afbba6f5d366f96297028aa3d64512fa254a51
This commit is contained in:
37
files.qip
37
files.qip
@ -1,20 +1,20 @@
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set_global_assignment -name QIP_FILE rtl/T80/T80.qip
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set_global_assignment -name VERILOG_FILE rtl/memory/dma.v
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set_global_assignment -name VERILOG_FILE rtl/memory/arbiter.v
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set_global_assignment -name VERILOG_FILE rtl/memory/sdram.v
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set_global_assignment -name VERILOG_FILE rtl/memory/dpram.v
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set_global_assignment -name VERILOG_FILE rtl/common/zsignals.v
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set_global_assignment -name VERILOG_FILE rtl/common/zports.v
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set_global_assignment -name VERILOG_FILE rtl/common/zmem.v
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set_global_assignment -name VERILOG_FILE rtl/common/zmaps.v
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set_global_assignment -name VERILOG_FILE rtl/common/zint.v
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set_global_assignment -name VERILOG_FILE rtl/common/zclock.v
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set_global_assignment -name VERILOG_FILE rtl/rtc/mc146818a.v
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set_global_assignment -name VERILOG_FILE rtl/common/clock.v
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set_global_assignment -name VERILOG_FILE rtl/common/dma.v
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set_global_assignment -name VERILOG_FILE rtl/common/resetter.v
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set_global_assignment -name VERILOG_FILE rtl/common/spi.v
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set_global_assignment -name VERILOG_FILE rtl/dram/arbiter.v
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set_global_assignment -name VERILOG_FILE rtl/dram/dpram.v
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set_global_assignment -name VERILOG_FILE rtl/dram/sdram.v
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set_global_assignment -name VERILOG_FILE rtl/periph/kempston_mouse.v
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set_global_assignment -name VHDL_FILE rtl/periph/keyboard.vhd
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set_global_assignment -name VERILOG_FILE rtl/periph/mc146818a.v
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set_global_assignment -name VERILOG_FILE rtl/periph/vdac.v
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set_global_assignment -name VHDL_FILE rtl/sound/soundrive.vhd
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set_global_assignment -name QIP_FILE rtl/sound/jt12/jt03.qip
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/turbosound.sv
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set_global_assignment -name VERILOG_FILE rtl/sound/gs.v
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/saa1099.sv
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set_global_assignment -name VERILOG_FILE rtl/sound/gs.v
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/compressor.sv
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set_global_assignment -name VERILOG_FILE rtl/video/video_ts_render.v
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set_global_assignment -name VERILOG_FILE rtl/video/video_ts.v
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@ -25,10 +25,11 @@ set_global_assignment -name VERILOG_FILE rtl/video/video_out.v
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set_global_assignment -name VERILOG_FILE rtl/video/video_mode.v
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set_global_assignment -name VERILOG_FILE rtl/video/video_fetch.v
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set_global_assignment -name VERILOG_FILE rtl/video/video_top.v
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set_global_assignment -name VHDL_FILE rtl/keyboard.vhd
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set_global_assignment -name VERILOG_FILE rtl/kempston_mouse.v
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set_global_assignment -name VERILOG_FILE rtl/spi.v
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set_global_assignment -name VERILOG_FILE rtl/clock.v
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set_global_assignment -name VERILOG_FILE rtl/z80/zclock.v
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set_global_assignment -name VERILOG_FILE rtl/z80/zint.v
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set_global_assignment -name VERILOG_FILE rtl/z80/zmaps.v
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set_global_assignment -name VERILOG_FILE rtl/z80/zmem.v
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set_global_assignment -name VERILOG_FILE rtl/z80/zports.v
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set_global_assignment -name VERILOG_FILE rtl/z80/zsignals.v
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set_global_assignment -name VERILOG_FILE rtl/tsconf.v
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set_global_assignment -name SDC_FILE TSConf.sdc
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set_global_assignment -name SYSTEMVERILOG_FILE TSConf.sv
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set_global_assignment -name SEARCH_PATH rtl/
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