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zint: cleanup.

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sorgelig
2018-08-23 04:18:58 +08:00
parent 5d9db127a9
commit 0f9f64b632
1 changed files with 5 additions and 19 deletions
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24
src/cpu/zint.v
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@ -10,7 +10,7 @@ module zint
input wire vdos, input wire vdos,
input wire intack, input wire intack,
input wire [7:0] intmask, input wire [7:0] intmask,
output wire [7:0] im2vect, output reg [7:0] im2vect,
output wire int_n output wire int_n
); );
@ -18,21 +18,7 @@ module zint
// For Frame, Line INT its generation is blocked, it will be lost. // For Frame, Line INT its generation is blocked, it will be lost.
// For DMA INT only its output is blocked, so DMA ISR will will be processed as soon as returned from VDOS. // For DMA INT only its output is blocked, so DMA ISR will will be processed as soon as returned from VDOS.
assign im2vect = {vect[int_sel]}; assign int_n = ~(int_frm || int_lin || int_dma) | vdos;
// ~INT source latch
localparam INTFRM = 2'd0;
localparam INTLIN = 2'd1;
localparam INTDMA = 2'd2;
localparam INTWTP = 2'd3;
wire [7:0] vect [0:3];
assign vect[INTFRM] = 8'hFF;
assign vect[INTLIN] = 8'hFD;
assign vect[INTDMA] = 8'hFB;
assign vect[INTWTP] = 8'hFF;
assign int_n = ~((int_frm || int_lin || int_dma) && !vdos);
wire dis_int_frm = !intmask[0]; wire dis_int_frm = !intmask[0];
wire dis_int_lin = !intmask[1]; wire dis_int_lin = !intmask[1];
@ -45,9 +31,9 @@ always @(posedge clk) intack_r <= intack;
reg [1:0] int_sel; reg [1:0] int_sel;
always @(posedge clk) begin always @(posedge clk) begin
if (intack_s) begin if (intack_s) begin
if (int_frm) int_sel <= INTFRM; // priority 0 if (int_frm) im2vect <= 8'hFF; // priority 0
else if (int_lin) int_sel <= INTLIN; // priority 1 else if (int_lin) im2vect <= 8'hFD; // priority 1
else if (int_dma) int_sel <= INTDMA; // priority 2 else if (int_dma) im2vect <= 8'hFB; // priority 2
end end
end end