set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt03.v                 ]
set_global_assignment -name VHDL_FILE    [file join $::quartus(qip_path) jt12.vhd               ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_top.v             ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt03_acc.v             ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_single_acc.v      ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_eg.v              ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_eg_cnt.v          ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_eg_comb.v         ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_eg_step.v         ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_eg_pure.v         ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_eg_final.v        ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_eg_ctrl.v         ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_exprom.v          ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_kon.v             ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_lfo.v             ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_mmr.v             ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_div.v             ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_mod.v             ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_op.v              ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_csr.v             ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_pg.v              ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_pg_inc.v          ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_pg_dt.v           ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_pg_sum.v          ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_pg_comb.v         ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_pm.v              ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_logsin.v          ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_reg.v             ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_reg_ch.v          ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_sh.v              ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_sh_rst.v          ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_sh24.v            ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_sumch.v           ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_timers.v          ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_dout.v            ]
set_global_assignment -name QIP_FILE     [file join $::quartus(qip_path) ../jt49/jt49.qip       ]
